Patents by Inventor James G. Fiorenza
James G. Fiorenza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240097016Abstract: Integrated circuits can include compound semiconductor devices having conductive components that control electrical characteristics of the compound semiconductor devices. In one or more examples, one or more conductive components can be located to increase the concentration of electrons in relation to a source electrical contact or a drain electrical contact. In one or more additional examples, a conductive component can be located to reduce the concentration of electrons in relation to a gate electrical contact. The compound semiconductor devices can include a number of compound semiconductor layers that include one or more materials having at least one Group 13 element and at least one Group 15 element.Type: ApplicationFiled: December 2, 2021Publication date: March 21, 2024Inventors: James G. Fiorenza, Daniel Piedra, Joshua Andrew Perozek
-
Publication number: 20230377882Abstract: During gallium nitride (GaN) semiconductor fabrication, a nucleation layer, e.g., aluminum nitride (AlN) may be formed superjacent a substrate, e.g., silicon carbide (SiC). Next, a semiconductor layer, such as including GaN, may be formed over the nucleation layer. This disclosure describes various techniques for forming a thick enough layer of gallium nitride (GaN) to ensure complete coalescence and minimal surface roughness, then removing the excess GaN until a desired thickness is achieved. In some examples, the GaN removal may be performed by desorption, such as may be performed in-situ by using hydrogen gas close to the growth temperature.Type: ApplicationFiled: May 12, 2023Publication date: November 23, 2023Inventors: James G. Fiorenza, Daniel Piedra
-
Publication number: 20230317801Abstract: A semiconductor device includes a layer of a first semiconducting material, where the first semiconducting material is epitaxially grown to have a crystal structure of a first substrate. The semiconductor device further includes a layer of a second semiconducting material disposed adjacent to the layer of the first semiconducting material to form a heterojunction with the layer of the first semiconducting material. The semiconductor device further includes a first component that is electrically coupled to the heterojunction, and a second substrate that is bonded to the layer of the first semiconducting material.Type: ApplicationFiled: June 7, 2023Publication date: October 5, 2023Inventors: Puneet Srivastava, James G. Fiorenza
-
Publication number: 20230299156Abstract: In one or more implementations, a semiconductor device can include a first compound semiconductor device coupled to a second compound semiconductor device coupled in a face-to-face arrangement. The first compound semiconductor device can be coupled to the second compound semiconductor device such that a cavity is formed that includes a first gate electrical contact of the first compound semiconductor device and a second gate electrical contact of the second compound semiconductor device. A gap can be present between the first gate electrical contact and the second gate electrical contact.Type: ApplicationFiled: September 14, 2021Publication date: September 21, 2023Inventors: James G. Fiorenza et al., Daniel Piedra
-
Publication number: 20230299172Abstract: Techniques are described for forming a sealed cavity within a semiconductor wafer, where a conductor wafer includes a structure, such as a T-gate electrode or passive component, formed over a substrate. The sealed-cavity structure may be embedded into the wafer without interfering with any subsequent processes. That is, once the cavity is closed, any subsequent backend processes may continue as usual.Type: ApplicationFiled: March 17, 2022Publication date: September 21, 2023Inventors: Yingqi Jiang, James G. Fiorenza
-
Publication number: 20230154875Abstract: Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.Type: ApplicationFiled: December 30, 2022Publication date: May 18, 2023Inventors: Daniel Piedra, James G. Fiorenza, Puneet Srivastava, Andrew Proudman, Kenneth Flanders, Denis Michael Murphy, Leslie P. Green, Peter R. Stubler
-
Publication number: 20230141865Abstract: A lateral GaN superjunction transistor or switching device that is configured to have higher breakdown voltage and lower on-resistance as compared to other GaN-based switching devices. The lateral GaN superjunction transistor includes a heavily doped buried implant region (hereinafter, “buried implant region”) in the substrate underlying the transistor that operates as backside field plate (BFP) to control or reduce gate-drain electric fields at the surface of the transistor, thereby enabling the transistor to operate at higher voltages while reducing charge trapping and breakdown effects. The lateral GaN superjunction transistor operates similarly to a vertical silicon superjunction FET to enable operation of the transistor at higher voltages than other GaN or semiconductor devices, such as to enable the construction of faster or higher power electronic circuits.Type: ApplicationFiled: October 25, 2022Publication date: May 11, 2023Inventors: James G. Fiorenza, Daniel Piedra, Leonard Shtargot, F. Jacob Steigerwald
-
Publication number: 20230133481Abstract: Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.Type: ApplicationFiled: December 30, 2022Publication date: May 4, 2023Inventors: Daniel Piedra, James G. Fiorenza, Puneet Srivastava, Andrew Proudman, Kenneth Flanders, Denis Michael Murphy, Leslie P. Green, Peter R. Stubler
-
Patent number: 11637096Abstract: A hybrid silicon carbide (SiC) device includes a first device structure having a first substrate comprising SiC of a first conductivity type and a first SiC layer of the first conductivity type, where the first SiC layer is formed on a face of the first substrate. The first device structure also includes a second SiC layer of a second conductivity type that is formed on a face of the first SiC layer and a first contact region of the first conductivity type, where the first contact region traverses the second SiC layer and contacts the first SiC. The device also includes a second device structure that is bonded to the first device structure. The second device structure includes a switching device formed on a second substrate and a second contact region that traverses a first terminal region of the switching device and contacts the first contact region.Type: GrantFiled: June 10, 2022Date of Patent: April 25, 2023Assignee: Analog Devices, Inc.Inventors: James G. Fiorenza, Puneet Srivastava, Daniel Piedra
-
Publication number: 20230122090Abstract: Electric field management techniques in GaN based semiconductors that utilize patterned regions of differing conductivity under the active GaN device, such as a GaN high electron mobility transistor (HEMT), are described. As an example, a patterned layer of oxidized silicon can be formed superjacent a layer of silicon dioxide during or prior to the heteroepitaxy of GaN or another semiconductor material. These techniques can be useful for back-side electric field management because a silicon layer, for example, can be made conductive to act as a back-side field plate.Type: ApplicationFiled: October 18, 2021Publication date: April 20, 2023Inventors: James G. Fiorenza, Daniel Piedra
-
Publication number: 20230058073Abstract: A semiconductor device includes a layer of a first semiconducting material, where the first semiconducting material is epitaxially grown to have a crystal structure of a first substrate. The semiconductor device further includes a layer of a second semiconducting material disposed adjacent to the layer of the first semiconducting material to form a heterojunction with the layer of the first semiconducting material. The semiconductor device further includes a first component that is electrically coupled to the heterojunction, and a second substrate that is bonded to the layer of the first semiconducting material.Type: ApplicationFiled: October 19, 2022Publication date: February 23, 2023Inventors: Puneet Srivastava, James G. Fiorenza
-
Patent number: 11569182Abstract: Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.Type: GrantFiled: October 1, 2020Date of Patent: January 31, 2023Assignee: Analog Devices, Inc.Inventors: Daniel Piedra, James G. Fiorenza, Puneet Srivastava, Andrew Proudman, Kenneth Flanders, Denis Michael Murphy, Leslie P. Green, Peter R. Stubler
-
Patent number: 11538709Abstract: A transfer printing method is described that can be used for a wide variety of materials, such as to allow for circuits formed of different materials to be integrated together on a single integrated circuit. A tether (18) is formed on dice regions (16) of a first wafer (30), followed by attachment of a second wafer (32) to the tethers. The dice regions (16) are processed so as to be separated, followed by transfer printing of the dice regions to a third wafer (34).Type: GrantFiled: February 17, 2018Date of Patent: December 27, 2022Assignee: Analog Devices International Unlimited CompanyInventors: James G. Fiorenza, Susan L. Feindt, Michael D. Delaus, Matthew Duffy, Ryan Iutzi, Kenneth Flanders, Rama Krishna Kotlanka
-
Patent number: 11508821Abstract: A semiconductor device includes a layer of a first semiconducting material, where the first semiconducting material is epitaxially grown to have a crystal structure of a first substrate. The semiconductor device further includes a layer of a second semiconducting material disposed adjacent to the layer of the first semiconducting material to form a heterojunction with the layer of the first semiconducting material. The semiconductor device further includes a first component that is electrically coupled to the heterojunction, and a second substrate that is bonded to the layer of the first semiconducting material.Type: GrantFiled: May 10, 2018Date of Patent: November 22, 2022Assignee: Analog Devices, Inc.Inventors: Puneet Srivastava, James G. Fiorenza
-
Publication number: 20220310578Abstract: A hybrid silicon carbide (SiC) device includes a first device structure having a first substrate comprising SiC of a first conductivity type and a first SiC layer of the first conductivity type, where the first SiC layer is formed on a face of the first substrate. The first device structure also includes a second SiC layer of a second conductivity type that is formed on a face of the first SiC layer and a first contact region of the first conductivity type, where the first contact region traverses the second SiC layer and contacts the first SiC. The device also includes a second device structure that is bonded to the first device structure. The second device structure includes a switching device formed on a second substrate and a second contact region that traverses a first terminal region of the switching device and contacts the first contact region.Type: ApplicationFiled: June 10, 2022Publication date: September 29, 2022Inventors: James G. Fiorenza, Puneet Srivastava, Daniel Piedra
-
Patent number: 11393806Abstract: A hybrid silicon carbide (SiC) device includes a first device structure having a first substrate comprising SiC of a first conductivity type and a first SiC layer of the first conductivity type, where the first SiC layer is formed on a face of the first substrate. The first device structure also includes a second SiC layer of a second conductivity type that is formed on a face of the first SiC layer and a first contact region of the first conductivity type, where the first contact region traverses the second SiC layer and contacts the first SiC. The device also includes a second device structure that is bonded to the first device structure. The second device structure includes a switching device formed on a second substrate and a second contact region that traverses a first terminal region of the switching device and contacts the first contact region.Type: GrantFiled: September 14, 2020Date of Patent: July 19, 2022Assignee: Analog Devices, Inc.Inventors: James G. Fiorenza, Puneet Srivastava, Daniel Piedra
-
Patent number: 11355598Abstract: A semiconductor device having a back-side field plate includes a buffer layer that includes a first compound semiconductor material, where the buffer layer is epitaxial to a crystalline substrate. The semiconductor device also includes field plate layer that is disposed on a surface of the buffer layer. The semiconductor device further includes a first channel layer disposed over the field plate layer, where the first channel layer includes the first compound semiconductor material. The semiconductor device further includes a region comprising a two-dimensional electron gas, where the two-dimensional electron gas is formed at an interface between the first channel layer and a second channel layer. The semiconductor device additionally includes a back-side field plate that is formed by a region of the field plate layer and is electrically isolated from other regions of the field plate layer.Type: GrantFiled: July 3, 2019Date of Patent: June 7, 2022Assignee: Analog Devices, Inc.Inventors: Puneet Srivastava, James G. Fiorenza, Daniel Piedra
-
Publication number: 20220093779Abstract: An enhancement mode compound semiconductor field-effect transistor (FET) includes a source, a drain, and a gate located therebetween. The transistor further includes a first gallium nitride-based hetero-interface located under the gate and a buried region, located under the first hetero-interface, the buried p-type region configured to determine an enhancement mode FET turn-on threshold voltage to permit current flow between the source and the drain.Type: ApplicationFiled: September 11, 2019Publication date: March 24, 2022Inventors: James G. Fiorenza, Puneet Srivastava, Daniel Piedra
-
Publication number: 20210134641Abstract: A transfer printing method is described that can be used for a wide variety of materials, such as to allow for circuits formed of different materials to be integrated together on a single integrated circuit. A tether (18) is formed on dice regions (16) of a first wafer (30), followed by attachment of a second wafer (32) to the tethers. The dice regions (16) are processed so as to be separated, followed by transfer printing of the dice regions to a third wafer (34).Type: ApplicationFiled: February 17, 2018Publication date: May 6, 2021Inventors: James G. Fiorenza, Susan L. Feindt, Michael D. Delaus, Matthew Duffy, Ryan lutzi, Kenneth Flanders, Rama Krishna Kotlanka
-
Publication number: 20210126120Abstract: Integrated circuits can include semiconductor devices with back-side field plates. The semiconductor devices can be formed on substrates that have conductive layers located within the substrates. The conductive layers can include at least one of a conducting material or a semi-conducting material that modifies an electric field produced by the semiconductor devices. The semiconductor devices can include one or more semiconductor layers that include one or more materials having a compound material that includes at least one Group 13 element and at least one Group 15 element.Type: ApplicationFiled: October 12, 2020Publication date: April 29, 2021Inventors: Daniel Piedra, James G. Fiorenza, Puneet Srivastava