Abstract: A circuit and method for generating a substantially smooth clock for clocking asynchronous data to a user device. Incoming asynchronous data is stored in an elastic buffer such as a first-in first-out memory. Periodically, an output identifiable bit is read into the memory and a multibit digital signal corresponding to the number of output clock pulses for it to be read out is determined. This signal, which corresponds to the occupancy of the first-in first-out memory, is used to generate an analog voltage which controls a voltage controlled oscillator that provides the substantially smooth clock for reading data out of the first-in first-out memory. The control loop causes the long term rate of the smooth clock to be substantially equal to the incoming asynchronous data rate.