Abstract: A process for reworking the upper level metal layer of an integrated circuit wafer having multiple levels of metal connected by vias through intermediate dielectric layers. In one form, a photoresist masking layer is first formed over the defective upper level metal using an expanded reverse field pattern of the vias. The wafer is then subjected to a metal etch to completely remove the exposed upper level metal while etching into the metal under the photoresist until the etching enters the metal in the via. Thereafter, the residual photoresist is removed. The rework process is concluded with a single chamber operation composed of a sputter etch followed by the deposition of new upper level metal. The concluding chamber sequence ensures the proper via metal surface conditioning for reliable deposition bonding of the new upper level metal deposited thereon.