Abstract: A power management system has a primary power source (100) and a secondary power source (106) generated from the primary power source (100) with a power output selector (204) coupled to each for selecting power for a regulated power output (212). First, during initialization and at any other time during operation, when the primary power source (102) exceeds the secondary power source (106), the primary power source (102) is used as a power supply for the regulated power output (212). Second, at any time after initialization that the primary power source (102) exceeds the regulated power output (212), the primary power source (102) is used as the power supply for the regulated power output (212). Third, at any time after initialization that the secondary power source (106) exceeds the primary power source (106) and the primary power source (102) is less than the regulated power output (212), the secondary power source (106) is used as the power supply for the regulated power output (212).

Abstract: A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal and a discrete time clock generator that generates an output pulse in response to receiving an assertion of the first data clock. The output pulse is asserted for a fixed duration that is independent of a jitter of the first data clock. The digital-to-analog converter also includes a continuous time analog output that produces, during assertion of the output pulse, a continuous time analog output signal having a magnitude corresponding to the digital signal samples.

Abstract: A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal and a discrete time clock generator that generates an output pulse in response to receiving an assertion of the first data clock. The output pulse is asserted for a fixed duration that is independent of a jitter of the first data clock. The digital-to-analog converter also includes a continuous time analog output that produces, during assertion of the output pulse, a continuous time analog output signal having a magnitude corresponding to the digital signal samples.

Abstract: A selective call receiver (500) includes a radio receiver (501) and a processor (508). The radio receiver includes an antenna (502), a combination circuit (204), a bandpass filter (208), mixers (212, 214), analog-to-digital converters (222, 224), digital mixers (234, 236), a second combination circuit (242), and a digital-to-analog converter (246). The combination circuit receives an analog signal from the antenna and combines the same with an analog feedback signal generated by the digital-to-analog converter. The bandpass filter filters the output of the combination circuit and supplies its output to the mixers which down-convert the signal to baseband signals. These signals are modified by the analog-to-digital converters to digital signals which are up-converted by the digital mixers. The outputs of the digital mixers are combined by the second combination circuit to a digital output that is modified by the digital-to-analog converter to the analog feedback signal.

Abstract: A sigma delta analog-to-digital converter (100) comprising a second or third order integrator block (105) featuring a feed-forward connection path between the input of the integrator block and an input of at least one of the plurality of integrators (130 or 150). A comparator (180) coupled to the output of the integrator block (105) generates as output a digital value representing a difference between the integrator output signal with respect to a threshold, or in a differential mode implementation, between component signals of a differential signal output by the integrator block (105). A digital sampling element (190) coupled to the output of the comparator (180) samples the output of the comparator (180) in response to a sampling clock signal at a predetermined sampling frequency to generate as output digital signal comprising samples of the digital values output by the comparator (180).

Abstract: A communication system (100) for selectively providing repeat messages includes a message transmission device (105) for normally transmitting messages a single time, for receiving repeat requests indicating that a previously transmitted message should be transmitted again, and for automatically transmitting future messages more than once in response to determining that a number of repeat requests exceeds a transmission threshold. A radio communication device (110) is included in the communication system (100) for receiving the messages and for generating a repeat request in response to determining that the previously transmitted message has not been correctly received.

Abstract: An oscillator circuit (143) comprises a master phase-locked loop (PLL) circuit (202) that receives as input a first reference frequency signal (136) and generates a first clock signal (210) in response to an oscillator control signal (212). The oscillator circuit (143) includes a frequency sensitive slave circuit (206) having at least one frequency sensitive element (322) that is responsive to a tracking control signal (214) to generate a second clock signal (216). A tracking control circuit (204) is responsive to the oscillator control signal (212) for generating the tracking control signal (214). The tracking control signal (214) serves as a bias signal, and is connected to the frequency sensitive slave circuit (206) for achieving a fast power up sequence of the oscillator circuit (143).

Abstract: A voltage regulator circuit (100) for coupling to a power supply voltage (BPLUS) generates and regulates an output voltage (VREG). The voltage regulator circuit (100) includes a gain control element (148) for controlling the loop gain of the voltage regulator circuit (100) in response to the output current. Under heavy load conditions, the gain control element (148) functions to reduce (716) the output voltage (VREG) and thus the output current of the voltage regulator circuit (100) to avoid an overload that would pull the power supply voltage (BPLUS) below a predetermined level.

Abstract: A battery saving apparatus selectively supplies power to the receiver functions of a battery powered communication receiver at predetermined time intervals prior to the reception of coded message signal. The selective supplying of power to the receiver functions enables the reception of the coded message signal with the receiver functions being powered prior to and only as long as is required for the receiver functions to stabilize and to enable reception of a coded message signal. The predetermined time intervals for the receiver functions are programmed into a code plug to provide the capability to change the turn-on times when required.

Abstract: A data recovery device (208) for recovering data symbols having a period T from a received data stream. The data recovery device samples at least one data symbol in the received data stream at a rate determined by an integration envelope (301) having the period T. The samples are accumulated as a weighted sample count representing a recovered data symbol that is then stored as at least one recovered data bit.

Abstract: A filter (13) for providing temperature compensation for the quality factor thereof comprises transconductance amplifiers (23 and 24) in a gyrator configuration coupled between an input node (21) and an output node (22). A parallel capacitor (25) is coupled between the input node (21) and a supply voltage, and a parallel resistor (26) is coupled between the input node (21) and the supply voltage. A series capacitor (27) is coupled to the output node (22), and a series resistor (28) is coupled between the second capacitor (27) and the supply voltage.

Abstract: A battery saving apparatus selectively supplies power to each receiver function of a battery powered communication receiver at predetermined time intervals prior to and continuing therefrom for enabling the reception of the coded message signals with each receiver function being powered only as long as is required for each receiver function to stabilize prior to the reception of the coded message signals.

Abstract: A selective call receiver (100) includes a receiver (1104) for receiving a signal. The receiver (104) includes a controlled filter (142) having a variable frequency response. A decoder (106) coupled to the controlled filter (142) of the receiver (104) decodes the received signal. The decoder (106) has a decoder clock for generating a decoder clock signal (122). A controlled oscillator (134) has an input filter (136) controlled by a control signal (132). The controlled oscillator (134) generates an output signal (140) in response to the control signal (132) for coupling to a comparator (124) which generates the control signal (126) from the decoder clock signal (122) and the output signal (140). The control signal (126) is further coupled to the controlled filter(142) for controlling the frequency response of the controlled filter (142) which filters the received signal.

Abstract: In a heterodyne receiver having more than one selectable receive frequency and having at least one intermediate frequency circuit (102) capable of operation on at least two intermediate frequencies, a method for selecting one of the at least two intermediate frequencies is shown. The selection method includes selecting (402) one of the more than one selectable receive frequency, and then selecting (408, 410, 504, 506, 510, 512) at least one of the at least two intermediate frequencies for each of the at least one intermediate frequency circuit in response to the selected receive frequency. The selection of the intermediate frequency for each of the at least one intermediate frequency circuit is made such that the selected intermediate frequency does not cause the generation of one or more undesirable spurious frequencies as a result of mixing the selected receive frequency and the selected intermediate frequency.

Abstract: A symbol synchronizer for a communication receiver receiving multi-level data signals includes a reference clock generator for generating a reference clock signal having a predetermined time period, a state change detector for detecting state changes occurring within the received multi-level data signals over the predetermined time period to enable determining a time location corresponding to the detected state change wherein the time locations are assigned predetermined numeric values corresponding to the time locations determined, an accumulator for accumulating a time location for the time locations selected, and a phase adjusting circuit which is responsive to the time location count for adjusting the phase of the reference clock signal relative to the received multi-level data signal.

Abstract: A paging receiver is provided which digitizes and stores received analog voice messages. The stored voice message may be retrieved by using a first switch for a normal playback mode, or by using a second switch for a fast forward and fast reverse playback mode. The fast forward and fast reverse playback modes are achieved by sequentially retrieving every N(th) message bit stored in memory.

Abstract: A receiver (200) includes an automatic frequency controller that determines the frequency of a receiver signal, and a calculates a frequency error from the received signal. The frequency error is used to calculate a correction factor (316) that is used to adjust the frequency of an oscillator (308) in response to the determined error.

Abstract: An electrical circuit (200) comprises a first circuit (208) constructed and arranged to simulate an inductor and a second circuit (210) constructed and arranged to simulate an inductor. Coupled to these circuits is a third circuit (212) for simulating a mutual inductance therebetween.

Abstract: A voltage potential monitoring circuit is operative to set a voltage potential threshold substantially independent of ambient temperature variation. The monitoring circuit includes a first circuit for generating a first current proportional to the voltage potential being monitored, and a second circuit responsive to the first circuit for generating a second current. The voltage potential threshold is set substantially as a function of the first and second currents. The monitoring circuit further includes a circuit responsive to the first and second currents for generating an undervoltage signal when the monitored voltage potential falls below the set voltage potential threshold. The voltage potential monitoring circuit has application in an electronic device which is operational over an ambient temperature range and includes a source of power for generating a voltage potential suitable for energizing the electronic device.

Abstract: A battery saver type paging receiver includes an improved peak and valley amplitude detection type data limiter section with mode control operation thereof, digital word storage of acquired peak and valley amplitude values, and self tuning capabilities. More specifically, the data limiter section includes a controller for controlling the peak and valley detection circuits to acquire respective peak and valley amplitude values in digital word form in a first operational mode and to hold the peak and valley amplitude digital words in corresponding storage registers in a second operational mode. The controller may transfer the data limiter section into a third operational mode during which the peak and valley digital words may be altered a predetermined count to effect a self-tuning thereof. In one embodiment, the third mode of operation is effected during the transfer between the second and first modes of operation.