Abstract: A storage controller is configured to determine a reliability metric of a storage division of a solid-state storage medium based on one or more test read operations. The storage division may be retired based on the reliability metric and/or the age of the data on the storage division. A storage division comprising aged data may be marked for post-write reliability testing, which may comprise determining a post-write reliability metric in response to grooming and/or reprogramming the storage division. The storage controller may project the reliability metric of the storage division to the end of a predetermined data retention period. Portions of a storage divisions that exhibit poor reliability may be removed to improve the reliability of the storage division without taking the entire storage division out of service.

Abstract: A storage layer is configured to store data at respective offsets within storage units of a storage device. Physical addresses of the data may be segmented into a first portion identifying the storage unit in which the data is stored, and a second portion that indicates the offset of the data within the identified storage unit. An index of the data offsets (e.g., second portions of the physical addresses) may be persisted on the storage device. The first portion of the address may be associated with logical addresses of the data in a forward index. The forward index may omit the second portion of the physical addresses, which may reduce the memory overhead of the index and/or allow the forward index to reference larger storage devices. Data of a particular logical address may be accessed using the first portion of the physical address maintained in the forward index, and the second portion of the media address stored on the storage device.

Abstract: An auto-commit memory is capable of implementing a pre-configured, triggered commit action in response to a failure condition, such as a loss of power, invalid shutdown, fault, or the like. A computing device may access the auto-commit memory using memory access semantics (using a memory mapping mechanism or the like), bypassing system calls typically required in virtual memory operations. Since the auto-commit memory is pre-configured to commit data stored thereon in the event of a failure, users of the auto-commit memory may view these memory semantic operations as being instantly committed. Operations to commit the data are taken out of the write-commit path.

Abstract: A method and apparatus for storing data packets in two different logical erase blocks pursuant to an atomic storage request is disclosed. Each data packet stored in response to the atomic storage request comprises persistent metadata indicating that the data packet pertains to an atomic storage request. In addition, a method and apparatus for restart recovery is disclosed. A data packet preceding an append point is identified as satisfying a failed atomic write criteria, indicating that the data packet pertains to a failed atomic storage request. One or more data packets associated with the failed atomic storage request are identified and excluded from an index of a non-volatile storage media.

Abstract: Data of a vector storage request pertaining to one or more disjoint, non-adjacent, and/or non-contiguous logical identifier ranges are stored contiguously within a log on a non-volatile storage medium. A request consolidation module modifies one or more sub-requests of the vector storage request in response to other, cached storage requests. Data of an atomic vector storage request may comprise persistent indicators, such as persistent metadata flags, to identify data pertaining to incomplete atomic storage requests. A restart recovery module identifies and excludes data of incomplete atomic operations.

Abstract: An auto-commit memory is capable of implementing a pre-configured, triggered commit action in response to a failure condition, such as a loss of power, invalid shutdown, fault, or the like. A computing device may access the auto-commit memory using memory access semantics (using a memory mapping mechanism or the like), bypassing system calls typically required in virtual memory operations. Since the auto-commit memory is pre-configured to commit data stored thereon in the event of a failure, users of the auto-commit memory may view these memory semantic operations as being instantly committed. Since operations to commit the data are taken out of the write-commit path, the performance of applications that are write-commit bound may be significantly improved.

Abstract: Camera system and methods to capture panoramic imagery from a camera mounted on a moving platform, using low-cost digital image sensors. The panoramic imagery appears seamless and natural to the eye. The panoramic imaging system and methods are specifically designed to accommodate the long acquisition times of low-cost digital image sensors, despite the motion of the camera during image capture. Pairs of cameras are arranged about an axis and a pairwise firing sequence enables capturing a series of adjacent images without gap or overlap. Additionally, when combined with suitable supplemental sensors, the image data provide location information about objects in the image for use in elementary photogrammetry.

Abstract: A computer is programmed to identify types of variables, in a computer program which includes a number of variables that are used without any explicit indication of their type, by repeatedly performing at least propagation of types from variables' definitions to variables' uses and removal of unreachable code. Repetition of type propagation from definitions to uses and removal of unreachable code is one aspect of the invention. The repetition can be terminated differently in different embodiments. In many embodiments, the repetition is performed until no unreachable code is found.

Abstract: A memory circuit in which are stored multiple sets of upper and lower limits that are simultaneously compared with a stream of input data words. The data words and the upper and lower limits may be selectively segmented into data fields or dimensions, and match signals are generated if the input data fields fall within the corresponding fields of the upper and lower limits. The match signals may be selectively masked by a window enable register, and the data fields selected by changing a field length control register.

Abstract: A monolithic convolver circuit making extensive use of "pipelined" architecture to ensure high speed by concurrency of processing, and having a repetitive stage to facilitate chip layout and manufacture. The circuit includes a multiplier and an adder in each stage. The adders produce a sequence of summation terms concurrently and include shift registers to move and accumulate the results of convolution. The adders produce only partial sums at each stage, to increase processing speed. Full computation of carries is deferred until the very end, and performed in a separate conditional sum adder.

Abstract: A parallel analog-to-digital converter having high speed and high resolution, fabricated on a single integrated-circuit chip in such a manner as to avoid problems typically associated with high speed parallel converters. The converter disclosed by way of example has an eight-bit output, 256 matched comparators for quantizing an analog input signal, and encoding and latching logic for deriving digital outputs from the comparators. Problems related to comparator mismatching, high comparator input capacitance and high comparator input bias current, are effectively minimized by the use of a triple diffusion fabrication process, which substantially reduces the number of defects in the circuit and provides a relatively high component packing density.

Abstract: A sensitive high speed clocked comparator for use with low level differential logic circuits which utilizes an amplifier, a Gilbert Gain Cell, and load devices to amplify the difference between analog voltages being compared, and a high speed latch to increase the output voltage level of the Gain Cell up to the level of logic signals used in low level differential logic circuits. The circuit has two modes, a "follow" mode wherein the amplifier and Gilbert Gain Cell cause an unbalance in the currents through two load devices responsive to any difference in input voltage, and a "latch" mode wherein a latch causes the current unbalance to increase and to latch. The modes are sequentially selected by clocking.