Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract: Implementing a key and a protection circuit in a configurable device. A soft key associated with a protection circuit is combined with a user's electronic design in generating configuration data for download onto the configurable device. The placement and routing of the soft key is pseudo-randomly arranged with respect to the user's electronic design such that its placement and routing on the configurable device is substantially different for binary configuration data that is generated. Hiding the soft key and its connections to the protection circuit and assisting in protecting user electronic designs is achieved.

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract: In an example embodiment, an EDA program receives input which includes a selection as to an FPGA die and its device package and a selection as to a structured ASIC die and its device package. If the I/O pins on the device package for the FPGA differ from the I/O pins on the device package for the structured ASIC, the EDA program determines a correspondence between the I/O pins on the two device packages (e.g., by identifying the location of the pads for I/O pins on the structured ASIC die and/or creating a virtual structured ASIC device package whose I/O pins are a superset of the I/O pins on the selected structured ASIC device package), which determination includes checking rules for resource assignments. The EDA program then stores the determined correspondence in a device database where the determined correspondence can be accessed by CAD algorithms.

Abstract: Compiler flows are provided that can produce functionally equivalent field programmable gate arrays (“FPGAs”) and structured application-specific integrated circuits (“structured ASICs”). The flows may include feeding back design transformations that are performed during either flow so that a later performance of the other flow will necessarily include the same transformations, thereby helping to ensure functional equivalence. The flows may include a comparison of intermediate results in order to prove that functional equivalence is being achieved.

Abstract: A programmable logic device having a Logic Element with an N-stage Look Up Table (LUT), dedicated hardware for performing a non-LUT logic function, and an over-ride element configured to selectively force a muxing stage within the N-stage LUT to select either one or more LUT configuration bit inputs or the output of the non-LUT logic function as the output of the LUT. In various embodiments, the non-LUT functions can include addition, subtraction, multiplication, division, digital signal processing, memory storage, etc.

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract: Circuits and methods use clock gating to reduce power consumption in select parts of a structured ASIC. A clock distribution network includes a deterministic portion, a configurable portion, and one or more clock gating circuits. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal and a clock enable signal to a plurality of predetermined locations on the device. A clock gating circuit, connected with the deterministic portion, may be placed at any of the predetermined locations, or at any location within predetermined areas associated with the predetermined locations. The clock gating circuit produces a gated clock signal output. A configurable portion and/or subportion distributes the gated clock signal output to logic elements. Depending on the value of the clock enable signal, operation of the logic elements may be suspended.

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract: The present invention is directed to a programmable logic device and a method of programming a programmable logic device that features providing a verification technique to ensure the requisite functional operations of an array of configurable logic blocks may be programmed while limiting a user from altering the functional operations of the configurable logic blocks of the programmable logic device to having functional operations in addition to and/or different from the functional operations of that a vendor desires a user to have. In this manner, the array of configurable logic blocks can be designed so that the same may be programmed to provide one or more of multiple different functional operations, while limiting a user to a desired set of functional operations.

Abstract: A field programmable gate array includes a plurality of programmable logic blocks to implement one or more logic functions. The field programmable gate array includes a plurality of independent registers not associated with any specific one of the plurality of programmable logic blocks. The plurality of independent registers may be programmed to support any one of the plurality of programmable logic blocks.

Abstract: Methods for facilitating the synthesis of structured ASICs that are functionally equivalent to FPGAs make use of the synthesis of a user's logic design for the FPGA. Each of several relatively small parts of the user's logic as synthesized for the FPGA technology is resynthesized for the structured ASIC implementation. The resynthesis may handle different kinds of parts of the logic differently. For example, for a part for which an ASIC synthesis is already known and available in a library, the known ASIC synthesis may be retrieved from the library. More extensive resynthesis (including, for example, logic minimization and function packing) may be performed on other parts of the logic for which library syntheses are not available.

Abstract: The present invention, generally speaking, relates to taking advantage of existing outputs from logic groupings that neighbor a digital signal processing block in a programmable logic device to expand the functionality of the digital signal processing block. The outputs from the logic groupings are used as dedicated routing interconnects that provide additional inputs into the digital signal processing block (e.g., into function specific blocks) such that the signal processing block receives additional signals. These additional signals can be input into the signal processing block via the dedicated routing interconnect without significant addition of input interconnection resources that are silicon-area expensive.

Abstract: An FPGA equivalent of a structured ASIC implementation of a user's logic design is produced by taking advantage of various aspects of the way in which the structured ASIC implementation was produced. For example, the structured ASIC breaks the user's logic design down into blocks that are readily implemented in basic units of the FPGA circuitry. Starting from such an acceptable ASIC mapping of the user's logic, resynthesis for FPGA implementation can be performed, at least as a first step, on a block-by-block basis. The FPGA implementation can then be made more economical and efficient by looking for blocks that can be combined in individual basic units of the FPGA circuitry.

Abstract: Compiler flows are provided that can produce functionally equivalent field programmable gate arrays (“FPGAs”) and structured application-specific integrated circuits (“structured ASICs”). The flows may include feeding back design transformations that are performed during either flow so that a later performance of the other flow will necessarily include the same transformations, thereby helping to ensure functional equivalence. The flows may include a comparison of intermediate results in order to prove that functional equivalence is being achieved.

Abstract: A method for improving the performance of a computer logic simulator in a computer system in which the operation of a logic design is simulated by converting a network list representative of the logic design into a simulator netlist and applying predetermined input vectors to the simulator netlist representative of the logic design in order to generate output vectors representative of the response of the simulator netlist. Portions of the network list are converted to dynamic device models in the form of executable code, which is assembled in a dynamic device model file. The remaining portions of the network list are converted to a simulator netlist, which is stored in a simulator netlist file. Both the dynamic device models and the simulator netlist are used to perform the simulation process.

Abstract: A method for improving the performance of a computer logic simulator in a computer system in which the operation of a logic design is simulated by converting a network list representative of the logic design into a simulator netlist and applying predetermined input vectors to the simulator netlist representative of the logic design in order to generate output vectors representative of the response of the simulator netlist. Portions of the network list are converted to dynamic device models in the form of executable code, which is assembled in a dynamic device model file. The remaining portions of the network list are converted to a simulator netlist, which is stored in a simulator netlist file. Both the dynamic device models and the simulator netlist are used to perform the simulation process.