Abstract: A system for providing one or more services at a network access point is described. The system comprises a controller, a wireless interface coupled with the controller, a network interface coupled with the controller, at least one of an internal interface coupled with the controller and an external interface coupled with the controller, and at least one of one or more internal modules coupled with the internal interface and one or more external modules coupled with the external interface.

Abstract: The disclosed embodiments relate to an optimized memory registration mechanism that may comprise an upper layer protocol that associates I/O buffers with memory regions and that manages steering tags. The memory regions may be associated with a translation page table. The upper layer protocol may allocate one of the steering tags associated with at least one of the memory regions for a memory operation.

Abstract: A system for providing one or more services at a network access point is described. The system comprises a controller, a wireless interface coupled with the controller, a network interface coupled with the controller, at least one of an internal interface coupled with the controller and an external interface coupled with the controller, and at least one of one or more internal modules coupled with the internal interface and one or more external modules coupled with the external interface.

Abstract: A fly-by checksum is generated at a lower layer of the protocol stack and travels up to a high layer of a protocol stack to verify incoming data. In one embodiment, a network adapter comprises includes one or more protocol stacks and a LAN controller that includes a fly-by checksum generation unit. A checksum algorithm is registered with the fly-by checksum generation unit for each protocol layer that is to receive a fly-by checksum. As an incoming packet is transferred from network media to network adapter memory, the fly-by checksum generation unit calculates a fly-by checksum for each checksum algorithm that has been registered. After the fly-by checksums are complete, they are transmitted to the network adapter memory and are transmitted up the appropriate protocol stack within a checksum channel. When data reaches a layer of the protocol stack for which the fly-by checksum was generated, the fly-by checksum is removed from the checksum channel and is used to verify the integrity of the data.

Abstract: A peripheral system includes (a) a peripheral device having peripheral memory located thereon, (b) at least one input/output (I/O) card communicating with the peripheral device, and (c) a means for managing the peripheral memory between the peripheral device and the at least one I/O card. In a preferred embodiment, the means for managing the peripheral memory includes (a) a means for determining, during normal operation, an optimum amount of peripheral memory for allocating to each I/O card, and (b) a means for allocating, during normal operation, the optimum amount of peripheral memory to each I/O card. A preferred method for managing memory, between a peripheral device, having peripheral memory thereon, and at least one input/output (I/O) card, includes (a) determining, during normal operation, an optimum amount of peripheral memory for allocating to each I/O card, and (b) allocating, during normal operation, the optimum amount of peripheral memory to each I/O card.

Abstract: A packet-based communication system is described for linking a peripheral unit (PU) to the outside world via a communications link. The system includes a modular interface unit (MIU) which has a memory shared by processors in both the PU and MIU. The system employs control packets, read packets and write packets and performs a method for allocating the shared memory that optimizes memory utilization. The system determines a ratio of read to write packets required in the operation of the PU, and it ignores that ratio if the communications link will not transmit write packets. If the communication link will transmit write packets, it allocates read and write packet space within the shared memory in accordance with the ratio. The system also includes apparatus for enabling MIU configuration via user/keyboard inputs through the PU with the MIU providing the question and answer messages.