Abstract: A wiring structure with crossover capability is disclosed. The wiring utilizes a connection stud in a contact layer, beneath the plane of the otherwise-intersecting lines as a crossover. Thus, a first wire in a first metallization layer passes below a second wire in a second metallization layer by overlapping contact with the connection stud in the contact layer. In manufacturing the wiring structure of the present invention, no intervening insulative or via layers are used between the contact layer, the first metallization layer and the second metallization layer. However, care must be taken in device layout on the substrate to ensure that the connection stud is located above isolation areas rather than active device areas.

Abstract: A final passivation structure for a semiconductor device having conductive lines formed on a surface of the semiconductor device, comprising a planarized layer covering the surface and also covering the conductive lines, and a diffusion barrier covering the planarized layer. Alternately, the planarized layer may partially cover the conductive lines.

Abstract: A semiconductor device or other suitable substrate and method with single or multi layers of buried micro pipes are disclosed. This is achieved by controlling the aspect ratio of trenches as well as controlling the deposition characteristics of the material used to fill the trenches. A buried micro pipe is formed by filling a trench that has a height which is larger than a width thereof, so that the trench filler material lines sidewalls and bottom of the trench, and covers the top of the trench to form the micro pipe within the trench. Another layer can be formed over the filler material and planarized. Alternatively, the filler material itself can be planarized. Forming trenches in the planarized layer, and repeating the above steps forms a second set of buried micro pipes in these new trenches. This forms a semiconductor device having multiple layer of buried micro pipes.

Abstract: An aid to the manipulation of microfabricated micro tools in manufacturing and assembly is disclosed. A sequence of micro tools and a manipulator are connected to one another via attachment links as a combination. The attachment links are optimized to readily allow severing of individual micro tools from the combination as needed. The manipulator provides an aid for handling the combination via probe, pliers, clasping, mating or other device. This facilitates human or machine interaction with the combination of micro tools, either for subsequent processing, or for the assembly of the micro tools into a completed product.

Abstract: A seamless micromechanical object is cast by forming a multilevel mold, filling the mold, and selectively removing the mold with respect to the micromechanical object. The mold can have a first level having a first opening therein, and a second level on the first level, the second level having a second opening therein, the second opening smaller than the first opening. The object may contain a controlled void, for example a micromechanical auger with a void formed therethrough to be used as a capillary to drain off fluids when the auger is in use.

Abstract: A semiconductor device or other suitable substrate and method with single or multi layers of buried micro pipes are disclosed. This is achieved by controlling the aspect ratio of trenches as well as controlling the deposition characteristics of the material used to fill the trenches. A buried micro pipe is formed by filling a trench that has a height which is larger than a width thereof, so that the trench filler material lines sidewalls and bottom of the trench, and covers the top of the trench to form the micro pipe within the trench. Another layer can be formed over the filler material and planarized. Alternatively, the filler material itself can be planarized. Forming trenches in the planarized layer, and repeating the above steps forms a second set of buried micro pipes in these new trenches. This forms a semiconductor device having multiple layer of buried micro pipes. Via holes may be etched to contact a micro pipe, or to inter connect micro pipes buried at different levels.

Abstract: A method of fabricating a self-aligned borderless contact in a semiconductor device. The semiconductor device includes a first conductor level, a patterned conductor level defining a pair of spaced apart conducting segments, and a dielectric insulating layer disposed between the first conductor level and the patterned conductor level, and over the pair of spaced apart conducting segments of the patterned conductor level. The method comprises the steps of etching a contact hole in a selected region of the dielectric insulating layer which lies above and is substantially aligned between the pair of the segments. The etching continues through the dielectric insulating layer so that a portion of the dielectric insulating layer remains between the contact hole and the first conductor level. A spacer is formed which lines the contact hole.

Abstract: An apparatus and method provide deposition on a surface by angled sputtering using a collimation grid having angled vanes which limit the distribution of trajectories of particles in at least one coordinate direction around a central axis oriented at an angle of less than 90.degree. to said surface; resulting in improved uniformity of deposition and/or selective favoring of deposition on surfaces at a high angle to the deposition surface (e.g. sidewalls). Substantially parallel orientation and uniform spacing of the sputtering target and deposition surface provides good uniformity of results over the deposition surface. The angled trajectories of sputtered particles provides improved deposition on sides of upstanding mandrel features and filling of recessed features of high aspect ratio, especially when the collimation grid is rotated about an axis generally perpendicular to the deposition surface.

Abstract: A process for ablation etching through one or more layers of dielectric materials while not etching an underlying conductive material layer comprises selecting parameters whereby the ablation process automatically stops when the conductive material layer is reached, or monitoring the process for end point detection of the desired degree of ablation. Parameters selected are the absorptivity of the dielectric layer versus that of the conductive material layer. End point detection includes monitoring radiant energy reflected from the workpiece or the content of the materials being ablated from the workpiece.

Abstract: A simplified crack stop formation compatible with shallow fuse etch processes which are utilized for modern low-cost redundancy designs using upper level metal fuses. A modified last level metallization (LLM) etch according to the invention allows a high-productivity single step bondpad/fuse/crack stop etch. The stack of metal films formed at the edge of the dicing channel is readily removed with a modified LLM etch prior to dicing causing the insulator films covering the dicing channel to be physically separated from the insulators coating the electrically active chip areas. The separation prevents cracks that could propagate through the insulators of the dicing channel in to the active chip.

Abstract: A process for ablation etching through one or more layers of dielectric materials while not etching an underlying conductive material layer comprises selecting parameters whereby the ablation process automatically stops when the conductive material layer is reached, or monitoring the process for end point detection of the desired degree of ablation. Parameters selected are the absorptivity of the dielectric layer versus that of the conductive material layer. End point detection comprises monitoring radiant energy reflected from the workpiece or the content of the materials being ablated from the workpiece.

Abstract: The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to decrease the latch-up susceptibility of an ESD structure by suppressing the injection of minority carriers that cause transistor action to occur. This is accomplished, for example, by using a metal contact to the n-substrate or n-well in place of or in parallel with the prior art p-diffusion. Using such a metal contact forms a Schottky Barrier Diode (SBD) with the ESD structure. Since the SBD is a majority-carrier device, negligible minority carriers are injected when the SBD is in forward bias, thereby reducing the likelihood of latch-up.

Abstract: An damascene x-ray mask comprises an oxide membrane layer having trenches formed therein defining an x-ray mask pattern. The trenches are filled with collimated, sputtered tungsten sputtered in a relatively high pressure environment. The result is a dense, low stress tungsten film completely filling the trenches. Damascene refers to the process by which the mask is formed. The mask is formed on a silicon substrate and then the substrate is etched away from the bottom side leaving substantially just the oxide layer and the collimated tungsten. The oxide layer is transparent to x-rays and the collimated tungsten layer is opaque to x-rays.

Abstract: A marker element is included in a deposition chamber. After use of the chamber to deposit films or coatings on workpieces, the chamber is cleaned to remove materials which may contaminate future processing of workpieces in the chamber. The composition of the gas exhausted from the chamber during the cleaning process is monitored, and a characteristic of the marker element is sensed. The cleaning gas is terminated in response to the sensed characteristic of the marker element having a predetermined value, such as a peak intensity or the return to a baseline value after peaking. The present invention effectively solves the problem of overcleaning or undercleaning the chamber based upon an estimated film thickness build up.

Abstract: An improved process for depositing a conductive thin film upon an integrated circuit substrate by collimated sputtering is disclosed. The sputtered films are alloys of aluminum; a preferred alloying metal is magnesium. The sputtered films of the invention have a more uniform orientation of grains than sputtered aluminum copper silicon alloy films. Such processes are especially useful in the fabrication of integrated circuit devices having aluminum alloy wiring elements.