Abstract: A twisted helically-shaped member (15) in the form of a twisted tie, twisted fastener, twisted wire or twisted rod; said twisted helically-shaped member (15) having an axial core (12) and a plurality of helical threads (13H) extending along the axial core (12); and wherein a variation in lead measurements along the length of at least one helical thread (13H), is less than a variation in pitch measurements along the lengths of the helical threads (13H); wherein the axial core (12) has a transverse cross-sectional area comprising two-fifths or less of the transverse circumscribed cross-sectional area of the helical threads (13H).

Abstract: A method for assessing the release performance of microcapsules comprising at least one volatile ingredient, the method comprising the steps of: a. applying a plurality of said microcapsules to an underlying surface; b. applying a kinetic frictional shear stress ? through a contact surface of a probe under a predefined load, a predefined contact surface area and a predefined shear rate to said plurality of microcapsules; and c. measuring the amount of the at least one volatile ingredient released per second from said microcapsules under said kinetic frictional shear stress ?.

Abstract: Method and means of manufacturing ties, fasteners and rods (15) having a plurality of longitudinal threads by forcing a coil of roll-profiled feed-wire made of steel (11) through a twisting-die made of plastic (1). Also described is: a twisting-die made of plastic (1) that is suitable for twisting profiled feed-wire (11) made of steel; a method of forming a plastic twisting die (1) using an driven tap (31) in the form of a twisted rod (15); and a helically-shaped member (15) having lead measurements (X) along the length of the helical thread that vary less than pitch measurements (Y) along the lengths of the helical threads.

Abstract: A twisted helically-shaped member (15) in the form of a twisted tie, twisted fastener, twisted wire or twisted rod; said twisted helically-shaped member (15) having an axial core (12) and a plurality of helical threads (13H) extending along the axial core (12); and wherein a variation in lead measurements along the length of at least one helical thread (13H), is less than a variation in pitch measurements along the lengths of the helical threads (13H); wherein the axial core (12) has a transverse cross-sectional area comprising two-fifths or less of the transverse circumscribed cross-sectional area of the helical threads (13H).

Abstract: Method and means of manufacturing ties, fasteners and rods (15) having a plurality of longitudinal threads by forcing a coil of roll-profiled feed-wire made of steel (11) through a twisting-die made of plastic (1). Also described is: a twisting-die made of plastic (1) that is suitable for twisting profiled feed-wire (11) made of steel; a method of forming a plastic twisting die (1) using an driven tap (31) in the form of a twisted rod (15); and a helically-shaped member (15) having lead measurements (X) along the length of the helical thread that vary less than pitch measurements (Y) along the lengths of the helical threads.

Abstract: At least one configurable circuit cell with a continuous active region includes at least one center subcell, a first-side subcell, and a second-side subcell. Each center subcell includes first and second pMOS transistors and first and second nMOS transistors. The first pMOS transistor has a first-pMOS-transistor gate, source, and drain. The first-pMOS-transistor source is coupled to a first voltage source. The second pMOS transistor has a second-pMOS-transistor gate, source, and drain. The second-pMOS-transistor source is coupled to the first voltage source. The first-pMOS-transistor drain and the second-pMOS-transistor drain are a same drain. The first nMOS transistor has a first-nMOS-transistor gate, source, and drain. The first-nMOS-transistor source is coupled to a second voltage source. The second nMOS transistor has a second-nMOS-transistor gate, source, and drain. The second-nMOS-transistor source is coupled to the second voltage source.

Abstract: A well tool with a housing has an actuator sleeve in the housing. The actuator sleeve has an internal shifting tool engaging profile. An actuator is in the housing. The actuator is responsive to a remote signal to move the actuator sleeve from a first position to a second position. A dog is in the housing, supported to couple the actuator sleeve to the actuator when the actuator sleeve is in the first position and unsupported to allow the actuator sleeve to uncouple from the actuator when the actuator sleeve is in the second position.

Abstract: Core-shell capsules suitable for perfuming a consumer product comprising a polymeric shell surrounding and encapsulating a perfume-containing oil core, the mean diameter (D50) of which capsules is about 5 to 250 microns and which capsule is adapted to be ruptured to release perfume contained in the core under a rupture force of less than 2 milli Newtons (mN).

Abstract: Method and apparatus for voltage level shifters (VLS) design in bulk CMOS technology. A multi-voltage circuit or VLS that operate with different voltage levels and that provides area and power savings for multi-bit implementation of level shifter design. A two-bit VLS to shift bits from a first voltage level logic to a second voltage level logic. The VLS formed with a first N-well in a substrate. The VLS formed with a second N-well in the substrate, adjacent to a side of the first N-well. The VLS formed with a third N-well in the substrate, adjacent to a side of the first N-well and opposite the second N-well. A first one-bit VLS circuit having a portion formed on the first N-well and a portion formed on the second N-well. A second bit VLS circuit having a portion formed on the first N-well and a portion formed on the third N-well.

Abstract: Method and apparatus for voltage level shifters (VLS) design in bulk CMOS technology. A multi-voltage circuit or VLS that operate with different voltage levels and that provides area and power savings for multi-bit implementation of level shifter design. A two-bit VLS to shift bits from a first voltage level logic to a second voltage level logic. The VLS formed with a first N-well in a substrate. The VLS formed with a second N-well in the substrate, adjacent to a side of the first N-well. The VLS formed with a third N-well in the substrate, adjacent to a side of the first N-well and opposite the second N-well. A first one-bit VLS circuit having a portion formed on the first N-well and a portion formed on the second N-well. A second bit VLS circuit having a portion formed on the first N-well and a portion formed on the third N-well.

Abstract: A multimode, uniform-latency clock generation circuit (CGC) is described herein. In one example, the multimode, uniform-latency CGC generates a pulse clock signal via a clock generation path responsive to a clock chopping signal being active and generates a phase clock signal via the same clock generation path responsive to the clock chopping signal being inactive. The clock chopping signal is activated responsive to a mode control input signal being in a first state and deactivated responsive to either the mode control input signal being in a second state or a plurality of clock enable signals being inactive. In one or more embodiments, a multimode, uniform-latency CGC is included in a microprocessor for providing pulse clock signals to inter-stage pulsed sequential storage elements when operating in a timing sensitive mode and for providing phase clock signals to the inter-stage pulsed sequential storage elements when operating in a timing insensitive mode.

Abstract: A method for referencing image data. Preferred methods include methods for linking, characterizing, searching, and navigating the image data, as aids to reviewing the image data.

Abstract: A multi-enabled clock gating circuit reduces clock enable setup time. In one example, the multi-enabled clock gating circuit comprises an OAI logic gate and a clock enable control circuit. The OAI logic gate is configured to generate a gated clock signal by inverting an input clock signal responsive to one of a timing-sensitive clock enable signal and a timing-insensitive clock enable signal being active. The clock enable control circuit is configured to prevent the OAI logic gate from receiving the timing-insensitive clock enable signal responsive to the timing-sensitive clock enable signal being active. In one or more embodiments, a multi-enabled clock gating circuit having reduced clock enable setup time may be included in an integrated circuit for implementing clock gating during different operating modes of the integrated circuit.

Abstract: A liquid detergent composition contains greater than 5% by weight of surfactant and an encapsulate containing greater than 10% by weight of active material in a hydrated cross-linked anionic gum matrix. The anionic gum is preferably an alginate. The active material is preferably a fragrance. The detergent composition is particularly suitable for use as a laundry liquid.

Abstract: A multiple-axis imaging system having individually-adjustable optical elements and a method for individually adjusting optical elements of the system. The system comprises a plurality of optical elements having respective optical axes and being individually disposed with respect to one another to image respective sections of an object, and a plurality of individually-operable positioning devices corresponding to respective optical elements for positioning the optical elements with respect to their respective optical axes. The positioning devices are specifically adapted to adjust the axial position, lateral position and angular orientation of the optical elements with respect to their respective optical axes. The system is particularly adapted for use as a microscope array, and the positioning devices may be micro-actuators.

Abstract: The present invention relates to a method of preventing and/or reducing malodours in an environment, comprising use of an encapsulated perfume, the perfume being encapsulated in capsules comprising perfume in an amount greater than 4% by weight of capsule, and an anionic gum, the method comprising the step of placing the capsules in gaseous contact with the environment, such that perfume released from the capsules prevents and/or reduces malodour in the environment. The capsules typically demonstrate efficient and consistent perfume release over an extended period of time e.g. up to about 85 days and conveniently provide a visual indication of expiration by a change in colour an size during use until a defined end point, when capsule life is exhausted. Also disclosed is a capsule including an emulsifying agent selected from non-ionic surfactants and/or anionic surfactants.

Abstract: A multiple-axis imaging system having individually-adjustable optical elements and a method for individually adjusting optical elements of the system. The system comprises a plurality of optical elements having respective optical axes and being individually disposed with respect to one another to image respective sections of an object, and a plurality of individually-operable positioning devices corresponding to respective optical elements for positioning the optical elements with respect to their respective optical axes. The positioning devices are specifically adapted to adjust the axial position, lateral position and angular orientation of the optical elements with respect to their respective optical axes. The system is particularly adapted for use as a microscope array, and the positioning devices may be micro-actuators.

Abstract: A method and a flip-flop is disclosed in which power consumption is reduced in a standby mode. In a first aspect, the flip-flop comprises a first latch adapted to be coupled to a first power supply and a second latch coupled to the first latch and adapted to be coupled to a second power supply. The first and second power supplies are independently controllable to minimize power consumption in a standby mode. In a second aspect, a method for minimizing the power consumption of a flip-flop is also disclosed. The flip-flop includes a first latch and a second latch coupled thereto. The method comprises providing a first independently controllable power supply coupled to the master latch; and providing a second independently controllable power supply coupled to the slave latch. The method further includes reducing the voltage of at least one of the first and second power supplies responsive to the detection of a power saving mode.

Abstract: A method and a flip-flop is disclosed in which power consumption is reduced in a standby mode. In a first aspect, the flip-flop comprises a first latch adapted to be coupled to a first power supply and a second latch coupled to the first latch and adapted to be coupled to a second power supply. The first and second power supplies are independently controllable to minimize power consumption in a standby mode. In a second aspect, a method for minimizing the power consumption of a flip-flop is also disclosed. The flip-flop includes a first latch and a second latch coupled thereto. The method comprises providing a first independently controllable power supply coupled to the master latch; and providing a second independently controllable power supply coupled to the slave latch. The method further includes reducing the voltage of at least one of the first and second power supplies responsive to the detection of a power saving mode.

Abstract: A method for referencing image data. Preferred methods include methods for linking, characterizing, searching, and navigating the image data, as aids to reviewing the image data.