Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a variable gain amplifier (VGA) device that includes a low-gain tuning section and a high-gain tuning section. The low-gain tuning section includes both resistor and transistor elements. The high-gain tuning section includes a transistor element and is activated when an output gain is greater than a predetermined threshold level. There are other embodiments as well.

Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a variable gain amplifier (VGA) device that includes a low-gain tuning section and a high-gain tuning section. The low-gain tuning section includes both resistor and transistor elements. The high-gain tuning section includes a transistor element and is activated when an output gain is greater than a predetermined threshold level. There are other embodiments as well.

Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a variable gain amplifier (VGA) device that includes a low-gain tuning section and a high-gain tuning section. The low-gain tuning section includes both resistor and transistor elements. The high-gain tuning section includes a transistor element and is activated when an output gain is greater than a predetermined threshold level. There are other embodiments as well.

Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.

Abstract: The present invention is directed to signal processing system and electrical circuits. According to various embodiments, a DLL system includes a delay line provides multiple output signals associated with different clock phases. The delay line may be adjusted using a pair of bias voltages. A phase detector systems generates the bias voltages using the multiple output signals from the delay line. The multiple output signals include signals associated with the first phase, the last phase, and two adjacent phases. There are other embodiments as well.

Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.

Abstract: In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.

Abstract: The present invention is directed to signal processing system and electrical circuits. According to various embodiments, a DLL system includes a delay line provides multiple output signals associated with different clock phases. The delay line may be adjusted using a pair of bias voltages. A phase detector systems generates the bias voltages using the multiple output signals from the delay line. The multiple output signals include signals associated with the first phase, the last phase, and two adjacent phases. There are other embodiments as well.

Abstract: The present invention is directed to signal processing system and electrical circuits. According to various embodiments, a DLL system includes a delay line provides multiple output signals associated with different clock phases. The delay line may be adjusted using a pair of bias voltages. A phase detector systems generates the bias voltages using the multiple output signals from the delay line. The multiple output signals include signals associated with the first phase, the last phase, and two adjacent phases. There are other embodiments as well.

Abstract: In one aspect, the present invention is directed to a technique of, and system for enhancing the performance of high-speed digital communications through a communications channel, for example a backplane. In this aspect of the present invention, a transmitter includes equalization circuitry to compensate for bandwidth limitations and reflections in high-speed digital communication systems. In one embodiment, the equalization circuitry is designed, programmed and/or configured to introduce intersymbol interference in order to improve the signal integrity in high-speed communications and enhance the operation and performance of such systems. In this regard, the equalization circuitry includes temporally overlapping leading and/or trailing taps (relative to the data (symbol) signal) to reduce, minimize, mitigate or effectively eliminate pre-cursor and/or post-cursor intersymbol interference due to, for example, bandwidth limitations and reflections in high-speed digital communication systems.

Abstract: In one aspect, the present invention is directed to a technique of, and system for enhancing the performance of high-speed digital communications through a communications channel, for example a backplane. In this aspect of the present invention, a transmitter includes equalization circuitry to compensate for bandwidth limitations and reflections in high-speed digital communication systems. In one embodiment, the equalization circuitry is designed, programmed and/or configured to introduce intersymbol interference in order to improve the signal integrity in high-speed communications and enhance the operation and performance of such systems. In this regard, the equalization circuitry includes temporally overlapping leading and/or trailing taps (relative to the data (symbol) signal) to reduce, minimize, mitigate or effectively eliminate pre-cursor and/or post-cursor intersymbol interference due to, for example, bandwidth limitations and reflections in high-speed digital communication systems.

Abstract: In one aspect, the present invention is directed to a technique of, and system for enhancing the performance of high-speed digital communications through a communications channel, for example a backplane. In this aspect of the present invention, a transmitter includes equalization circuitry to compensate for bandwidth limitations and reflections in high-speed digital communication systems. In one embodiment, the equalization circuitry is designed, programmed and/or configured to introduce intersymbol interference in order to improve the signal integrity in high-speed communications and enhance the operation and performance of such systems. In this regard, the equalization circuitry includes temporally overlapping leading and/or trailing taps (relative to the data (symbol) signal) to reduce, minimize, mitigate or effectively eliminate pre-cursor and/or post-cursor intersymbol interference due to, for example, bandwidth limitations and reflections in high-speed digital communication systems.

Abstract: In one aspect, the present invention is directed to a technique of, and system for enhancing the performance of high-speed digital communications through a communications channel, for example a backplane. In this aspect of the present invention, a transmitter includes equalization circuitry to compensate for bandwidth limitations and reflections in high-speed digital communication systems. In one embodiment, the equalization circuitry is designed, programmed and/or configured to introduce intersymbol interference in order to improve the signal integrity in high-speed communications and enhance the operation and performance of such systems. In this regard, the equalization circuitry includes temporally overlapping leading and/or trailing taps (relative to the data (symbol) signal) to reduce, minimize, mitigate or effectively eliminate pre-cursor and/or post-cursor intersymbol interference due to, for example, bandwidth limitations and reflections in high-speed digital communication systems.

Abstract: In one aspect, the present invention is directed to a technique of, and system for enhancing the performance of high-speed digital communications through a communications channel, for example a backplane. In this aspect of the present invention, a transmitter includes equalization circuitry to compensate for bandwidth limitations and reflections in high-speed digital communication systems. In one embodiment, the equalization circuitry is designed, programmed and/or configured to introduce intersymbol interference in order to improve the signal integrity in high-speed communications and enhance the operation and performance of such systems. In this regard, the equalization circuitry includes temporally overlapping leading and/or trailing taps (relative to the data (symbol) signal) to reduce, minimize, mitigate or effectively eliminate pre-cursor and/or post-cursor intersymbol interference due to, for example, bandwidth limitations and reflections in high-speed digital communication systems.

Abstract: The present invention relates in general to a method, apparatus, and article of manufacture for providing high-speed digital communications through a communications channel. In one aspect, the present invention employs adaptive or adjustable equalization circuitry and techniques in the transmitter and/or receiver to enhance the system performance of, for example, a system using the PAM-4 coding.

Abstract: The present invention relates in general to a method, apparatus, and article of manufacture for providing high-speed digital communications through a communications channel. In one aspect, the present invention employs crosstalk management techniques and structures that increase the system performance in channel communications.

Abstract: The present invention relates in general to a method, apparatus, and article of manufacture for providing high-speed digital communications through a communications channel. In one aspect, the present invention employs a variable rate back channel, incorporated within an existing communication that does not increase or adversely impact the transmission rate of data on the communication channel.

Abstract: The present invention relates in general to a method, apparatus, and article of manufacture for providing high-speed digital communications through a communications channel. In one aspect, the present invention employs variable delay FIR equalizer in the transmitter module to increase the system performance in channel communications.

Abstract: In one aspect, the present invention is directed to a technique of, and system for enhancing the performance of high-speed digital communications through a communications channel, for example a backplane. In this aspect of the present invention, a transmitter includes equalization circuitry to compensate for bandwidth limitations and reflections in high-speed digital communication systems. In one embodiment, the equalization circuitry is designed, programmed and/or configured to introduce intersymbol interference in order to improve the signal integrity in high-speed communications and enhance the operation and performance of such systems. In this regard, the equalization circuitry includes temporally overlapping leading and/or trailing taps (relative to the data (symbol) signal) to reduce, minimize, mitigate or effectively eliminate pre-cursor and/or post-cursor intersymbol interference due to, for example, bandwidth limitations and reflections in high-speed digital communication systems.

Abstract: In one aspect, the present invention is a system and technique that provides for the systematic development or implementation of codes that increase the robustness of systems employing, for example, PAM-n transmission techniques. The system and technique of this aspect of the invention eliminate, minimize, reduce or limit transitions between extreme signaling levels. As a result, the slew rate employed and/or required by the transmitter may reduce crosstalk and intersymbol interference, and provide for wider “eye” openings from the perspective of the receiver.