Patents by Inventor James Guilford

James Guilford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10719323
    Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Dan Baum, Michael Espig, James Guilford, Wajdi K. Feghali, Raanan Sade, Christopher J. Hughes, Robert Valentine, Bret Toll, Elmoustapha Ould-Ahmed-Vall, Mark J. Charney, Vinodh Gopal, Ronen Zohar, Alexander F. Heinecke
  • Patent number: 10691529
    Abstract: A processing device comprising compression circuitry to: determine a compression configuration to compress source data; generate a checksum of the source data in an uncompressed state; compress the source data into at least one block based on the compression configuration, wherein the at least one block comprises: a plurality of sub-blocks, wherein the plurality of sub-block includes a predetermined size; a block header corresponding to the plurality of sub-blocks; and decompression circuitry coupled to the compression circuitry, wherein the decompression circuitry to: while not outputting a decompressed data stream of the source data: generate index information corresponding to the plurality of sub-blocks; in response to generating the index information, generate a checksum of the compressed source data associated with the plurality of sub-blocks; and determine whether the checksum of the source data in the uncompressed format matches the checksum of the compressed source data.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: June 23, 2020
    Assignee: INTEL CORPORATION
    Inventors: Vinodh Gopal, James Guilford, Daniel Cutter, Kirk Yap
  • Publication number: 20200007329
    Abstract: Disclosed embodiments relate to encrypting or decrypting confidential data with additional authentication data by an accelerator and a processor. In one example, a processor includes processor circuitry to compute a first hash of a first block of data stored in a memory, store the first hash in the memory, and generate an authentication tag based in part on a second hash. The processor further includes accelerator circuitry to obtain the first hash from the memory, decrypt a second block of data using the first hash, and compute the second hash based in part on the first hash and the second block of data.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: James GUILFORD, Vinodh GOPAL, Kirk YAP
  • Publication number: 20200004535
    Abstract: An apparatus and method for loading and storing multiple sets of packed data elements.
    Type: Application
    Filed: June 30, 2018
    Publication date: January 2, 2020
    Inventors: KIRK YAP, JAMES GUILFORD, DANIEL CUTTER, VINODH GOPAL, DANIIL SOKOLOV
  • Publication number: 20190391869
    Abstract: A processing device comprising compression circuitry to: determine a compression configuration to compress source data; generate a checksum of the source data in an uncompressed state; compress the source data into at least one block based on the compression configuration, wherein the at least one block comprises: a plurality of sub-blocks, wherein the plurality of sub-block includes a predetermined size; a block header corresponding to the plurality of sub-blocks; and decompression circuitry coupled to the compression circuitry, wherein the decompression circuitry to: while not outputting a decompressed data stream of the source data: generate index information corresponding to the plurality of sub-blocks; in response to generating the index information, generate a checksum of the compressed source data associated with the plurality of sub-blocks; and determine whether the checksum of the source data in the uncompressed format matches the checksum of the compressed source data.
    Type: Application
    Filed: June 20, 2018
    Publication date: December 26, 2019
    Inventors: Vinodh Gopal, James Guilford, Daniel Cutter, Kirk Yap
  • Patent number: 10270464
    Abstract: An apparatus and method for performing efficient lossless compression.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: James Guilford, Kirk Yap, Vinodh Gopal, Daniel Cutter, Wajdi Feghali
  • Publication number: 20190042257
    Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.
    Type: Application
    Filed: September 27, 2018
    Publication date: February 7, 2019
    Inventors: Dan BAUM, Michael ESPIG, James GUILFORD, Wajdi K. FEGHALI, Raanan SADE, Christopher J. HUGHES, Robert VALENTINE, Bret TOLL, Elmoustapha OULD-AHMED-VALL, Mark J. CHARNEY, Vinodh GOPAL, Ronen ZOHAR, Alexander F. HEINECKE
  • Publication number: 20190042611
    Abstract: Technologies for determining unique values include a computing device that further includes one or more accelerator devices. Each accelerator device is to receive input data and query configuration data, the input data including a packed array of unsigned integers of column data from a database and the query configuration data including an element width of the input data, and generate, in response to receiving the query configuration data, a bit-map output table based on the query configuration data, generate a write request for each element of the input data to set a corresponding bit-map output bit of the bit-map output table which corresponds to an element value of the corresponding element. Subsequently, the accelerator device is further to set the corresponding bit-map output bit to indicate a presence of the corresponding element and output the bit-map output table indicative of unique elements that are present in the input data.
    Type: Application
    Filed: January 11, 2018
    Publication date: February 7, 2019
    Inventors: Kirk Yap, James Guilford, Daniel Cutter, Vinodh Gopal
  • Publication number: 20190034490
    Abstract: Technologies for determining set membership include a computing device that further includes one or more accelerator devices. Each accelerator device is to receive input data and definition table configuration data, the input data including a packed unsigned integers of column data from database and the definition table configuration data including a set membership query condition, generate a definition table indicative of element values that satisfy the set membership query condition, generate a lookup request for an element of the column data of the input data, perform the lookup request by accessing the definition table to determine whether the element satisfies the set membership query condition, and generate output indicative of whether the element is a member of the set membership.
    Type: Application
    Filed: December 28, 2017
    Publication date: January 31, 2019
    Inventors: Kirk Yap, James Guilford, Daniel Cutter, Vinodh Gopal
  • Publication number: 20190034493
    Abstract: Data element filter logic (“hardware accelerator”) in a processor that offloads computation for an in-memory database select/extract operation from a Central Processing Unit (CPU) core in the processor is provided. The Data element filter logic provides a balanced performance across an entire range of widths (number of bits) of data elements in a column-oriented Database Management System.
    Type: Application
    Filed: December 28, 2017
    Publication date: January 31, 2019
    Inventors: Vinodh GOPAL, Kirk S. YAP, James GUILFORD, Simon N. PEFFERS
  • Patent number: 9292283
    Abstract: Methods, systems, and apparatuses are disclosed for implementing fast large-integer arithmetic within an integrated circuit, such as on IA (Intel Architecture) processors, in which such means include receiving a 512-bit value for squaring, the 512-bit value having eight sub-elements each of 64-bits and performing a 512-bit squaring algorithm by: (i) multiplying every one of the eight sub-elements by itself to yield a square of each of the eight sub-elements, the eight squared sub-elements collectively identified as T1, (ii) multiplying every one of the eight sub-elements by the other remaining seven of the eight sub-elements to yield an asymmetric intermediate result having seven diagonals therein, wherein each of the seven diagonals are of a different length, (iii) reorganizing the asymmetric intermediate result having the seven diagonals therein into a symmetric intermediate result having four diagonals each of 7×1 sub-elements of the 64-bits in length arranged across a plurality of columns, (iv) adding all
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Erdinc Ozturk, Vinodh Gopal, James Guilford
  • Publication number: 20140189293
    Abstract: A processor is described having an instruction execution pipeline having a functional unit to execute an instruction that compares vector elements against an input value. Each of the vector elements and the input value have a first respective section identifying a location within data and a second respective section having a byte sequence of the data. The functional unit has comparison circuitry to compare respective byte sequences of the input vector elements against the input value's byte sequence to identify a number of matching bytes for each comparison. The functional unit also has difference circuitry to determine respective distances between the input vector ‘s elements’ byte sequences and the input value's byte sequence within the data.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Vinodh GOPAl, James GUILFORD
  • Publication number: 20140019725
    Abstract: Methods, systems, and apparatuses are disclosed for implementing fast large-integer arithmetic within an integrated circuit, such as on IA (Intel Architecture) processors, in which such means include receiving a 512-bit value for squaring, the 512-bit value having eight sub-elements each of 64-bits and performing a 512-bit squaring algorithm by: (i) multiplying every one of the eight sub-elements by itself to yield a square of each of the eight sub-elements, the eight squared sub-elements collectively identified as T1, (ii) multiplying every one of the eight sub-elements by the other remaining seven of the eight sub-elements to yield an asymmetric intermediate result having seven diagonals therein, wherein each of the seven diagonals are of a different length, (iii) reorganizing the asymmetric intermediate result having the seven diagonals therein into a symmetric intermediate result having four diagonals each of 7×1 sub-elements of the 64-bits in length arranged across a plurality of columns, (iv) adding all
    Type: Application
    Filed: December 6, 2012
    Publication date: January 16, 2014
    Inventors: ERDINC OZTURK, VINODH GOPAL, JAMES GUILFORD
  • Publication number: 20060150165
    Abstract: Systems and methods are disclosed for supporting virtual microengines in a multithreaded processor, such as a microengine running on a network processor. In one embodiment code is written for execution by a plurality of virtual microengines. The code is than compiled and linked for execution on a physical microengine, at which time the physical microengine's threads are assigned to thread groups corresponding to the virtual microengines. Internal next neighbor rings are allocated within the physical microengine to facilitate communication between the thread groups. The code can then be loaded onto the physical microengine and executed, with each thread group executing the code written for its corresponding virtual microengine.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 6, 2006
    Applicant: Intel Corporation
    Inventors: Donald Hooper, Prashant Chandra, James Guilford, Mark Rosenbluth
  • Publication number: 20050278707
    Abstract: A method and system to provide virtual resource usage information for assembler programs. In one embodiment, a graphical user interface displays virtual resource usage for portions of an assembler program.
    Type: Application
    Filed: June 9, 2004
    Publication date: December 15, 2005
    Inventor: James Guilford
  • Publication number: 20050273776
    Abstract: An assembler, which can form part of a development/debug system, supports pseudo instructions to enable the assembler to resolve return address ambiguities.
    Type: Application
    Filed: June 8, 2004
    Publication date: December 8, 2005
    Inventor: James Guilford
  • Publication number: 20050251795
    Abstract: Provided are a method, system, and program for optimizing code. A program is accessed comprising a plurality of instructions including at least one no operation (NOP) instruction. At least one NOP instruction in the program that is not needed to provide a processing delay to ensure data is available to at least one dependent instruction accessing the data is removed.
    Type: Application
    Filed: March 19, 2004
    Publication date: November 10, 2005
    Inventors: Mariano Fernandez, James Guilford
  • Publication number: 20050210457
    Abstract: An assembler, which can be provided as part of a debugger and/or development system, avoids register allocation errors, such as register bank conflicts and/or insufficient physical registers, automatically.
    Type: Application
    Filed: March 22, 2004
    Publication date: September 22, 2005
    Inventor: James Guilford
  • Publication number: 20050144413
    Abstract: Methods, software and systems to determine channel ownership and physical block location within the channel in non-uniformly distributed DRAM configurations and also to detect in-range memory address matches are presented. A first method, which may also be implemented in software and/or hardware, allocates memory non-uniformly between a number of memory channels, determines a selected memory channel from the memory channels for a program address, and maps the program address to a physical address within the selected memory channel. A second method, which may also be implemented in software and/or hardware, designates a range of memory to perform address matching, monitors memory accesses and when a memory access occurs with the specified range, perform a particular function.
    Type: Application
    Filed: December 30, 2003
    Publication date: June 30, 2005
    Inventors: Chen-Chi Kuo, Sridhar Lakshmanamurthy, Rohit Natarajan, Kin-Yip Liu, Prashant Chandra, James Guilford