Abstract: Data Integrity Field (DIF) is used to implement compression verification. When a write IO operation is received, the write IO operation is divided into data blocks, and a respective DIF is created and appended to each data block. When the write IO is compressed, the data blocks and respective DIF are collectively compressed to form compressed data. The compressed data is divided into compressed data blocks, and a respective second DIF is created and appended to each respective data block of compressed data. To verify that the compressed data is able to be decompressed, a copy of the compressed data is decompressed to restore the original data blocks and respective DIF. Each respective DIF is used to verify the content of its respective data block. In response to a determination that respective DIF match the respective data blocks, the decompression process is deemed to be verified.

Abstract: Methods and systems for managing systems based on power consumption are disclosed. To operate data processing systems, power may be supplied to the systems. Power supply capacity may be provisioned based on the estimated power consumption for the systems. To estimate the power consumption of the systems, limits on the operation of components of the systems may be taken into account. These limits may reduce the power consumption by the components from nominal power consumption ascribed by a manufacturer. The limits may be caused by the communication architecture or other features of the systems.

Abstract: A drive subset matrix is created with at least N+1 drives each having N*N same-size subdivisions. Conceptually, N submatrices are created along with spares equivalent to at least one drive of storage capacity. The spares are located such that every drive has an equal number of spares +/?1. One protection group is located in a lowest indexed subdivision of each of the submatrices. Members of other protection groups are located by selecting members in round robin order and placing each selected member in a free subdivision having a lowest drive index and lowest subdivision index. The drive subset can be grown, split, and reorganized to restore balanced and efficient distribution of spares.

Abstract: A drive subset matrix is created with at least N+1 drives each having N*N same-size subdivisions. Conceptually, N submatrices are created along with spares equivalent to at least one drive of storage capacity. The spares are located such that every drive has an equal number of spares +/?1. One protection group is located in a lowest indexed subdivision of each of the submatrices. Members of other protection groups are located by selecting members in round robin order and placing each selected member in a free subdivision having a lowest drive index and lowest subdivision index. The drive subset can be grown, split, and reorganized to restore balanced and efficient distribution of spares.

Abstract: A data storage system with multi-core processors dynamically enables and disables processor cores in order to manage power consumption while maintaining performance. One or more active processor cores are disabled responsive to determining that the current workload can be serviced with fewer active processor cores than are currently enabled while maintaining performance. One or more inactive processor cores are enabled responsive to determining that the current workload cannot be serviced with the currently active processor cores while maintaining performance. Separate utilization thresholds may be implemented for enabling inactive processor cores and disabling active processor cores to promote stability.

Abstract: A storage controller has an operating system (OS) and power control firmware configured to manage use of battery power during a power outage event. The OS specifies to the power control firmware first and second sets of physical components that should be shed by power control firmware during a two-phase vault process. Upon a power failure, the power control firmware turns off power to the first set of physical components and notifies the OS of the power failure. The OS determines whether to abort or continue the vault process. If the OS aborts the vault process, the power control firmware restores power to the first set of physical components. If the OS continues the vault process, the power control firmware turns off power to the second set of physical components, the OS saves application state, and moves all data from volatile memory to persistent memory.

Abstract: A storage controller has an operating system (OS) and power control firmware configured to manage use of battery power during a power outage event. The OS specifies to the power control firmware first and second sets of physical components that should be shed by power control firmware during a two-phase vault process. Upon a power failure, the power control firmware turns off power to the first set of physical components and notifies the OS of the power failure. The OS determines whether to abort or continue the vault process. If the OS aborts the vault process, the power control firmware restores power to the first set of physical components. If the OS continues the vault process, the power control firmware turns off power to the second set of physical components, the OS saves application state, and moves all data from volatile memory to persistent memory.

Abstract: A system may include a plurality processing cores for processing I/O operations and at least one interconnect component for communicatively coupling one or more external components to the plurality of processing cores. The at least one interconnect component may be directly physically connected to each of the plurality of processing cores. The interconnect component may route I/O operations to one of the processing cores based on a memory range of the I/O operation. An I/O communication including an I/O operation may be received at the interconnect component. The memory address range of the I/O operation may be determined. A processing core corresponding to the determined memory address range of the I/O operation may be determined, for example, by accessing a data structure that maps address ranges to processing cores. An I/O communication including the I/O operation may be sent from the interconnect component to the determined processing core.

Abstract: Metadata in volatile memory is selectively compressed and destaged to non-volatile storage in the event of an emergency shutdown due to loss of like power. Compression offload hardware that is normally used for data compression is used to compress the metadata, e.g. at line speed. The compressed metadata and any uncompressed metadata that was not selected for compression may be destaged to vault drives along with compressed and uncompressed data that is in the volatile memory. Compression during vaulting may decrease power consumption when operating under standby battery power.

Abstract: A storage system includes four storage engines, each storage engine including two compute nodes. Eight point-to-point connections are used to interconnect pairs of compute nodes on different storage engines, such that each compute node is connected to exactly two other compute nodes of the storage system. Atomic operations can be initiated by any compute node on any other compute node. Atomic operations received by a compute node on one of the point-to-point connections will be forwarded on the other point-to-point connection if the atomic operation is not directed to the compute node. During normal operation, atomic operations on a given compute node are performed on a host adapter associated with the compute node. Upon failure of the host adapter associated with the compute node, atomic operations may be performed on the compute node using the host adapter of the other compute node of the storage engine.

Abstract: Power conservation logic for a storage node operates in parallel with an emergency shutdown process in which an emergency power source is engaged and data and metadata are destaged from volatile memory to non-volatile managed drives. The power conservation logic serially implements power conservation actions until enough reserve power is available to complete the emergency shutdown process. The power conservation logic may learn how much power savings are realized from each conservation action and adjust the order in which the conservation actions are serially implemented, e.g. in order from greatest to least power consumption reduction.

Abstract: A storage system includes four storage engines, each storage engine including two compute nodes. Eight point-to-point connections are used to interconnect pairs of compute nodes on different storage engines, such that each compute node is connected to exactly two other compute nodes of the storage system. Atomic operations can be initiated by any compute node on any other compute node. Atomic operations received by a compute node on one of the point-to-point connections will be forwarded on the other point-to-point connection if the atomic operation is not directed to the compute node. During normal operation, atomic operations on a given compute node are performed on a host adapter associated with the compute node. Upon failure of the host adapter associated with the compute node, atomic operations may be performed on the compute node using the host adapter of the other compute node of the storage engine.

Abstract: Metadata in volatile memory is selectively compressed and destaged to non-volatile storage in the event of an emergency shutdown due to loss of like power. Compression offload hardware that is normally used for data compression is used to compress the metadata, e.g. at line speed. The compressed metadata and any uncompressed metadata that was not selected for compression may be destaged to vault drives along with compressed and uncompressed data that is in the volatile memory. Compression during vaulting may decrease power consumption when operating under standby battery power.

Abstract: A storage system includes four storage engines, each storage engine including two compute nodes. Eight point-to-point connections are used to interconnect pairs of compute nodes on different storage engines, such that each compute node is connected to exactly two other compute nodes of the storage system. Atomic operations can be initiated by any compute node on any other compute node. Atomic operations received by a compute node on one of the point-to-point connections will be forwarded on the other point-to-point connection if the atomic operation is not directed to the compute node. During normal operation, atomic operations on a given compute node are performed on a host adapter associated with the compute node. Upon failure of the host adapter associated with the compute node, atomic operations may be performed on the compute node using the host adapter of the other compute node of the storage engine.

Abstract: A system may include a plurality processing cores for processing I/O operations and at least one interconnect component for communicatively coupling one or more external components to the plurality of processing cores. The at least one interconnect component may be directly physically connected to each of the plurality of processing cores. The interconnect component may route I/O operations to one of the processing cores based on a memory range of the I/O operation. An I/O communication including an I/O operation may be received at the interconnect component. The memory address range of the I/O operation may be determined. A processing core corresponding to the determined memory address range of the I/O operation may be determined, for example, by accessing a data structure that maps address ranges to processing cores. An I/O communication including the I/O operation may be sent from the interconnect component to the determined processing core.

Abstract: Power conservation logic for a storage node operates in parallel with an emergency shutdown process in which an emergency power source is engaged and data and metadata are destaged from volatile memory to non-volatile managed drives. The power conservation logic serially implements power conservation actions until enough reserve power is available to complete the emergency shutdown process. The power conservation logic may learn how much power savings are realized from each conservation action and adjust the order in which the conservation actions are serially implemented, e.g. in order from greatest to least power consumption reduction.

Abstract: A storage system includes a storage engine having a first compute node, a second compute node, a first fabric adapter, and a second fabric adapter, the first compute node having a first memory and the second compute node having a second memory. The first compute node is connected to both the first and second fabric adapters, and the second compute node is connected to both the second and first fabric adapters. Both fabric adapters are configured to perform atomic operations on a memory of its respective compute node, and each fabric adapter contains a multi-initiating module configured to enable both the first compute node and the second compute node to initiate memory access operations on its respective memory.

Abstract: Selective use of a software path and hardware path help to provide fine-grained T10-PI support while maintaining IO operation efficiency for single IO read/write commands transferring multiple data segments. NVMe hardware capability (i.e. the hardware path) is always utilized for CPU-intensive CRC verification. NVMe hardware capability is utilized for application tag and reference tag verification whenever possible. Software running on a computing node (i.e. the software path) is used for application tag and reference tag verification and replacement when those functions cannot be implemented by the NVMe hardware.

Abstract: Selective use of a software path and hardware path help to provide fine-grained T10-PI support while maintaining IO operation efficiency for single IO read/write commands transferring multiple data segments. NVMe hardware capability (i.e. the hardware path) is always utilized for CPU-intensive CRC verification. NVMe hardware capability is utilized for application tag and reference tag verification whenever possible. Software running on a computing node (i.e. the software path) is used for application tag and reference tag verification and replacement when those functions cannot be implemented by the NVMe hardware.

Abstract: A method, computer program product, and computing system for identifying a low-write-frequency portion of a solid-state storage device. If it is determined that the low-write-frequency portion is of sufficient size to function as over-provisioning space for the solid-state storage device, the low-write-frequency portion is utilized as over-provisioning space.