Abstract: A method and associated system that compensates for long-term variations in the light-emitting efficiency of individual organic light emitting diodes (OLEDs) in an OLED display device, calculates and predicts the decay in light output efficiency of each pixel based on the accumulated drive current applied to the pixel and derives a correction coefficient that is applied to the next drive current for each pixel. In one exemplary embodiment of the invention, the calculation is based the accumulated current that has been passed through the device. In another exemplary embodiment, the calculation is based on a difference in voltage across the pixel at two instants. The compensation system is best used after the display device has been calibrated to provide uniform light output.

Abstract: A data driver circuit for an LCD including a switching circuit for transferring a data signal from a data channel to a first data line and a second data line. Also included is a sample circuit which alternately samples the data signal from the first data line and the second data line to produce and store respectively a first and second sampling data signal during a respective first and second time period. A data driver retrieves from the sample circuit the first sample data signal during the second time period and the second sampled data signal during the first time period. Then, the data driver transfers a driving pulse corresponding to one of the first sampled data signal and the second sampled data signal to the display.

Abstract: A liquid crystal display includes a base plate having a plurality of pixels on a surface thereof with the pixels arranged in an array of spaced rows and columns. Each of the pixels includes a substantially rectangular region of polycrystalline silicon. A separate select line of polycrystalline silicon extends over and across the polycrystalline silicon regions of each row of pixels adjacent one side of the polycrystalline silicon region. The select lines has two extensions extending over and along two opposite sides of each polycrystalline silicon region. A layer of a dielectric material extends between the polycrystalline silicon regions and the first lines and the extensions of the first lines. Each of the first lines and its extensions forms a capacitor with the respective polycrystalline silicon region of each pixel. Data lines extend along the rows of the pixels and are electrically connected to each polycrystalline silicon region in its respective column of pixels.

Abstract: A monolithic integrated circuit voltage regulator is disclosed in which a bipolar series pass transistor has both its collector and base electrodes protected from excessive positive and negative supply transients. Protection from positive voltage transients is provided by a reverse biased diode. Protection against negative voltage transients is provided by a bipolar transistor of opposite conductivity type from the pass transistor and a resistor in series therewith. The resistor is a diffused resistor comprising P-type material in an electrically isolated N-type well, resulting in blockage of negative voltage transients by both the transistor and the resistor.

Abstract: A method and apparatus for directly converting an analog photodiode signal to digital form using a switched capacitor successive approximation A/D converter. The charge extracted from a video line during a predetermined time interval by a photodiode is compared with charges successively injected onto the video line by a plurality of capacitors of decreasing capacitance value having a reference voltage sequentially impressed thereon. The voltage on the video line is compared with a threshold voltage for each of the capacitors, and the capacitor is returned to its previous state if it is found to have injected sufficient charge to increase the voltage on the video line to above the threshold voltage. The states of the capacitors at the conclusion of the process is a digital representation of the light intensity at the photodiode.

Abstract: A method and circuit are disclosed for detecting the state of a variable capacitor by comparator means whose threshold voltage is impressed on first plates of the variable capacitor and a reference capacitor having a capacitance between the minimum and maximum capacitances of the variable capacitor, and charging and discharging the second plates of the variable and reference capacitors by equal amounts in opposite senses. The voltage on the first plates of the capacitors then changes in a sense dependent on the relative capacitance values of the capacitors and is compared with the threshold voltage by the comparator means.

Abstract: A temperature compensation method and circuit for a Hall element or other element with similar characteristics comprising a pair of current carrying branches, one of which includes a resistor. A pair of transistors in the branches are controlled in unison to control the sum of the currents in the branches in response to current through the element, and controlled differentially to control the relative magnitudes of the currents in the branches in response to the voltage generated by the element. A comparator circuit including an active load in the branches compares the branch currents and provides a switched output signal upon a predetermined relationship between the currents. Switching hysteresis is provided by changing the sum of the currents depending on the state of the output signal.

Abstract: A first insulated-gate field-effect transistor (IGFET) having its conduction path connected between a first power terminal and an output terminal and a second IGFET of complementary conductivity to said first IGFET connected between the output terminal and a second power terminal. A selectively enabled level shift means coupled between the gate electrodes of the first and second IGFETs functions to substantially reduce the turn-on potential across the first transistor and to drive it off or to a high impedance state when a turn-on signal is applied to the second IGFET. The second IGFET can then easily and quickly drive the output to the voltage at the second power terminal. In response to an input turn-on signal for the first IGFET, it is pulsed on momentarily and the output is then clamped to the potential at the first power terminal.

Abstract: The circuit compensates for the difference in the source impedances of signal and reference generating circuits whose outputs are coupled to a sense circuit which loads (draws current from) the signal and reference generating circuits. The signal generating circuit has a source impedance (R.sub.1) and produces either one of two (V.sub.1H or V.sub.1L) output signal levels which is coupled via a first transmission gate having an "ON" impedance R.sub.2 to a first input terminal of the sense circuit. The reference generating circuit has a lower source impedance (R.sub.3) than the signal source and produces an output intermediate the two signal levels which is coupled via a second transmission gate having an "ON" impedance R.sub.4 to a second input terminal of the sense circuit. The reference voltage applied to the second input of the sense circuit is maintained at a predetermined level between the high and low levels of the signal applied to the first input of the sense circuit, by making the sum of R.sub.

Abstract: A voltage multiplier includes an inverter connected at its output to one plate of a capacitor for applying a first or a second voltage thereto, a first transistor switch which, when on, applies a second voltage to the second plate of the capacitor, and a second transistor switch which, when on, couples the second side of the capacitor to a load. For one polarity of input signal the inverter output switches from the first to the second voltage to produce an enhanced voltage at the second plate which is coupled via the second switch to the load. For the opposite polarity of input signal the inverter output switches from the second to the first voltage and the first switch is turned on.

Abstract: An inverting stage transfers binary signals from an input signal source to a latch circuit when the inverting stage and the latch are operated at similar voltages. Following data transfer, the operating voltage across the latch is increased. The inverting stage includes a diode which enables the transfer of binary signals between the inverting stage and the latch but which blocks the flow of current between them when the voltage across the latch is increased. The voltage levels of the output signals of the latch increase in correspondence with the increase in the operating voltage but the logic state to which the latch was set is maintained and there is no steady state current conduction between the inverting stage and the latch.

Abstract: A memory array of cells produces output signals having either one of a high value (i.e. V.sub.H) or a low value (i.e. V.sub.L). The difference between V.sub.H and V.sub.L is significantly less than the operating voltage (e.g. V.sub.DD) applied across the memory cells and V.sub.H and V.sub.L are offset towards one of the voltage rails (e.g. V.sub.DD or ground ). The memory cell output signals are compared to a reference signal (V.sub.R) derived either from a "dummy" cell or from a memory cell being sensed, where V.sub.R has a value which is less positive than V.sub.H but more positive than V.sub.L. The reference signal and a memory cell signal, are applied to a sense amplifier which is responsive to a relatively small difference between the two signals and which can produce an output (V.sub.O) which is approximately symmetrical with respect to the mid point (V.sub.DD /2) of the operating voltage. A signal (V.sub.H) more positive than V.sub.R causes V.sub.O to be more positive than V.sub.DD /2 and a signal (V.