Abstract: An integrated circuit device includes a peripheral control circuit configured to receive a low power intent signal from a first processor, and a first control register in the peripheral control circuit. The first control register includes a peripheral enable indicator for each processor that can use a first peripheral. Acknowledgement logic circuitry is configured to assert a first low power acknowledgement signal when the first processor issuing the low power intent signal has enabled use of the first peripheral as indicated by the peripheral enable indicator for the first processor in the first control register.

Abstract: An integrated circuit device includes a peripheral control circuit configured to receive a low power intent signal from a first processor, and a first control register in the peripheral control circuit. The first control register includes a peripheral enable indicator for each processor that can use a first peripheral. Acknowledgement logic circuitry is configured to assert a first low power acknowledgement signal when the first processor issuing the low power intent signal has enabled use of the first peripheral as indicated by the peripheral enable indicator for the first processor in the first control register.

Abstract: A digital tone generator (1110) includes a digital signal generator (1138) which generates a digital waveform data sequence which is representative of a tone having a predetermined waveform, and an adaptive duty cycle pulse-width modulator (1132) which is responsive to the digital waveform data sequence for generating an an adaptive duty cycle period characterized by a pulse-width modulated digital tone signal having a variable frequency and duty cycle which is generated by selecting a variable number of clock pulses of a predetermined reference clock (31).

Abstract: A digital tone generator (1110) includes a digital signal generator (1138) which generates a digital waveform data sequence which is representative of a tone having a predetermined waveform, and a pulse-width modulator (1132) which provides an adaptive duty cycle period (622, 630) which is responsive to the digital data waveform data sequence for selecting clock pulses of a number sufficient to generate a pulse-width modulated digital tone signal. The digital tone generator (110) can also include a low pass filter (36) which processes the pulse-width modulated digital tone signal to generate an analog tone signal. The digital waveform sequences generated by two digital tone generators (38, 40) can be digitally added by a digital adder (28) to provide a composite tone data signal, which can be processed by the adaptive pulse-width modulator (700) to produce a pulse-width modulated tone signal representative of a DTMF tone.

Abstract: Wafer level testing of a wafer (500) is accomplished by dividing the integrated circuits of the wafer into a plurality of segmented bus regions (514, 516, and 518 for example). Each bus region is formed having its own set of test conductors (520-530) wherein each set of test conductors are isolated from all other sets of test conductors on the wafer. Each test conductor has at least one contact pad (531-546) where each contact pad lies within a periphery of the integrated circuits' active areas. By forming pads over ICs and by sub-dividing the bus structure of test conductive lines, more high powered ICs can be tested in a wafer-level manner with fewer problems associated with speed, power, throughput, and routing problems.

Abstract: A semiconductor wafer (20) having integrated circuit dice (22), wafer conductors (42-47, 50-53), and wafer contact pads (38) formed thereon. The wafer conductors (42-47, 50-53) are used to transfer electrical signals to and from the integrated circuit dice (22) on semiconductor wafer (20) so that wafer level testing and burn-in can be performed on the integrated circuit dice (22). In accordance with one embodiment of the present, each wafer conductor (45, 52) is electrically coupled to the same bonding pad (78) on each integrated circuit dice (22). Each wafer conductor (42-47, 50-53) includes at least a portion of conductor (42-47) which overlies the upper surface of at least one integrated circuit dice (22).

Abstract: A semiconductor wafer (20) having integrated circuit dice (22), wafer conductors (42-47, 50-53), and wafer contact pads (38) formed thereon. The wafer conductors (42-47, 50-53) are used to transfer electrical signals to and from the integrated circuit dice (22) on semiconductor wafer (20) so that wafer level testing and burn-in can be performed on the integrated circuit dice (22). In accordance with one embodiment of the present, each wafer conductor (45, 52) is electrically coupled to the same bonding pad (78) on each integrated circuit dice (22). Each wafer conductor (42-47, 50-53) includes at least a portion of conductor (42-47) which overlies the upper surface of at least one integrated circuit dice (22).