Abstract: Video luminance data from a video signal is selectably compressed and expanded in a first signal path including a first line memory. A second line memory in a parallel signal path processes video chrominance data from the video signal. A control circuit generates respective timing signals for writing data into each of the first and second memories and for reading data from each of first and second the line memories. A timing delay circuit for the control circuit, has video compression and expansion modes of operation. During the compression mode, reading of the second line memory is delayed relative to writing of the second line memory. During the expansion mode, writing of the first line memory is delayed relative to writing of the second line memory or reading of the second line memory is delayed relative to writing of the second line memory. The duration of the timing delays can be selected from a range of values.

Abstract: Clock phase shifting circuitry includes a cascade connection of inverting amplifiers for generating a plurality of relatively delayed clock signals. Buffer amplifiers couple alternate ones of the inverting amplifiers to a clock phase selection circuit for providing a desired one of said plurality of delayed clock signals. A capacitor is coupled between the output of each inverting amplifier and a point of constant potential. Respective circuits, having an input impedance which emulates the input impedance of the buffer amplifiers, are coupled to the output connections of the inverting amplifiers located between said alternate inverting amplifiers.

Abstract: A phase-lock-loop circuit of a deflection apparatus generates a first signal at the horizontal frequency during normal operation. The first signal is coupled to a phase-control-loop circuit that maintains the deflection current timing in phase with the first signal. A fault protection circuit disables the generation of signal transitions in the first signal when a fault condition occurs. A circuit that detects the presence of transition edges in the first signal prevents the operation of the deflection output stage when the transition edges in the first signal are missing.

Abstract: An amplifier applies turn-on bias to the gate electrode of an output field-effect transistor in response to a first level of an input signal applied to the amplifier. A switched power source supplies operating current to the amplifier for developing the turn-on bias when the amplifier input signal is at the first level. A feedback-controlled bypass circuit diverts a portion of the operating current from the amplifier during an initial turn-on period and gradually reduces the magnitude of the diverted operating current as the output transistor turns on thereby producing a "soft" turn-on of the output transistor so as to minimize a potential for creating radio frequency interference in nearby RFI sensitive devices such as the tuner in a television or radio receiver. Complementary circuits include dual current supply and diversion circuits providing controlled rise and fall times for complementary field-effect output transistors.

Abstract: An amplifier having a resonator coupled between input and output terminals thereof supplies a dot clock signal to a character generator in a television receiver. A feedback control circuit supplies DC bias to the resonator during blanking intervals that preceed lines of characters to be displayed to ensure a consistent starting phase for oscillations, removes the DC bias and supplies operating power to the amplifier during a portion of the active video period of each displayed line for sustaining the oscillations and automatically inhibits the supply of amplifier power at the end of each active line of characters to thereby provide three oscillator operating modes of PRIMED, RUNNING and OFF so as to minimize overall power consumption for the oscillator for each field of displayed characters.

Abstract: A sensing circuit for determining the amplitude of an unknown impedance by comparing the voltage levels generated in a succession of current mirror circuits. In one form, the present circuit is connected to a ROM array comprised of FET devices having the potential of 2.sup.n different channel structures, impedances, to represent n different bits of data. When addressed, the selected ROM FET is coupled to a current mirror reference FET, whose commonly connected gate and drain electrodes are further coupled to a succession of 2.sup.n -1 current mirror FETs. Each of the current mirror FETs is connected in conductive series with an incrementally different impedance, the value of each impedance lying substantially midway between the 2.sup.n potential impedances possible in the ROM cell FET. The voltages on the current mirror FETs are individually compared to the voltage on the current mirror reference FET to generate a digital format representation of the relative magnitudes.