Abstract: A floating point arithmetic unit for performing independent multiply and add operations in the execution of a multiply-add instruction AC+B on three operands A, B, and C of p-bit precision includes a multiplier unit, a sticky collect unit, an adder unit, and a rounding unit. In addition, a risk condition detection unit provides detection of a risk condition corresponding to an occurrence of an imprecise resultant quantity prior to being rounded by the rounding unit. Upon detection of a risk condition, a trap is triggered and an extended sequence implementation unit carries out an extended multiply-add sequence and provides a multiply-add output having infinite precision prior to a final rounding. A floating point arithmetic method for performing independent multiply and add operations in the execution of a multiply-add instruction AC+B on three operands A, B, and C of p-bit precision is disclosed also.

Abstract: A high speed, compact low power integer adder unit for advanced microprocessors features modular construction, low gate count and a fast add time. A 64-bit implementation is characterized by a unique combination of dual rail logic circuits and dual carry select path within each of four 16-bit adder building blocks to achieve a one gate delay increment for each additional 16-bit adder building block after the first. Each of the 16-bit adder building blocks are composed of modules that receive four of sixteen bits of the operands, and each of the modules are comprised of submodules. The submodules are in turn comprised of dual rail logic circuits with a dual carry select path so as to constitute a nested carry select architecture wherein the nesting of the dual carry select path extends from submodules to a module and from modules to a basic building block.

Abstract: An apparatus performs source operand dependency analysis, perform register renaming and provide rapid pipeline recovery for a microprocessor capable of issuing and executing multiple instructions out-of-order in a single machine cycle. The apparatus first provides an enhanced means for rapid pipeline recovery due to a mispredicted branch or other store/load conflict or unsupported store/load forward circumstances. Second, the apparatus provides an improved instruction scheduling means wherein the oldest instructions that have all of their dependencies resolved are executed first. Third, the apparatus provides a means for enabling any execution or memory access instruction to execute out-of-order. Fourth, the apparatus provides a means for handling precise recovery of interrupts when processing instructions in out-of-order sequence.

Abstract: An apparatus to dynamically controls the out-of-order execution of load/store instructions by detecting a store violation condition and avoiding the penalty of a pipeline recovery process. The apparatus permits a load and store instruction to issue and execute out of order and incorporates a unique store barrier cache which is used to dynamically predict whether or not a store violation condition is likely to occur and, if so, to restrict the issue of instructions to the load/store unit until the store instruction has been executed and it is once again safe to proceed with out-of-order execution. The method implemented by the apparatus delivers performance within one percent of theoretically possible with apriori knowledge of load and store addresses.

Abstract: The machine method of the present embodiment relates to iterative numerical techniques adapted for use in digital circuitry, such as floating point multipliers and floating point adder-subtractor units. Using the Newton method of reciprocal computation of a value, several computational steps can be merged and performed with a single floating point multiplier unit. The preferred embodiment of the invention provides an improved method for computing the reciprocal of an unknown value C using Newton's method. The improved method forms the reciprocal Newton iteration in the following two steps:1. cx.sub.m form the product of x.sub.m and c.2. x.sub.m {2-cx.sub.m } form the product and difference simultaneously. Each step requires only the use of a multiplier-accumulator, and is more efficient and hence computationally faster than prior methods.

Abstract: The apparatus of the present embodiment relates to iterative numerical techniques adapted for use in digital circuitry, such as floating point multipliers and floating point adder-subtractor units. Using the Newton methods of reciprocal and reciprocal square root computations of a value, several computational steps can be merged and performed with a single floating point multiplier unit. The preferred embodiment of the invention provides an improved apparatus for computing the reciprocal and reciprocal square root of an unknown value C using Newton's method. The improved method forms the reciprocal Newton iteration in the following two steps: ##EQU1## Each step requires only the use of a multiplier-accumulator, and is more efficient and hence computationally faster than prior methods.

Abstract: A high-speed CMOS driver circuit which compensates for the intervening transmission line effects resulting from the existence of a printed circuit board, or a ceramic or silicon substrate between the coupled CMOS devices, thus preventing significant signal degradation. Several techniques are employed to increase circuit speed. Firstly, P-channel and N-channel output drivers are sized so that the characteristics impedance of each of the devices matches the characteristic impedance of its associated transmission line (whether it be on a printed circuit board or on a ceramic or silicon substrate). A printed circuit board transmission line may be of either the microstrip or stripline variety. Secondly, since P-channel and N-channel output drivers must be capable of delivering relatively high current, it is therefore highly desirable to eliminate or greatly reduce any crowbar current that could flow during the brief transition state when both N-channel and P-channel devices are on.

Abstract: The machine method of the present embodiment relates to iterative numerical techniques adapted for use in digital circuitry, such as floating- point multipliers and floating point adder-subtractor units. Using the Newton method of reciprocal square root computation of a value, several computational steps can be merged and performed with a single floating point multiplier unit.

Abstract: An area-efficient, low-noise transmission line structure for use in integrated circuits, which may be used to carry a high-frequency AC signal from a source location to one or more destination locations. This transmission line structure effectively decouples high-frequency signals carried by a signal line from a subjacent substrate. The structure comprises a dielectric layer subjacent the entire length of the signal line, a well of semiconductor material having a conductivity type opposite to that of the substrate, with the well being positioned beneath the signal line, extending substantially the entire distance between the source location and each destination location, being electrically insulated from the signal line by the dielectric layer, and forming a P-N junction with the substrate. The junction, which is maintained in a reverse-biased state, possesses a parasitic capacitance that is larger than the parasitic capacitance existing between the signal line and the well.

Abstract: A high-speed circuit that performs unsigned mode, two's complement mode, and mixed mode multiplication-accumulation with equal facility. The invention incorporates a high degree of regularity and interconnectivity. Speed is accomplished through interconnectivity, use of high speed adder elements, and a multiple-row addition technique.