Abstract: The present invention is directed to a method of controlling an etching process used to form a gate electrode on a semiconductor device. In one embodiment, the method comprises forming a layer of silicon dioxide above a semiconducting substrate, and forming a layer of polysilicon above the layer of silicon dioxide. The method further comprises sensing a thickness of the layer of polysilicon and adjusting, based upon the sensed thickness of said layer of polysilicon, at least one parameter of an etching process to be performed on said layer of polysilicon to define a gate electrode of a transistor, said etching process comprised of at least a timed etch process and an endpoint etch process.

Abstract: A method and an apparatus are provided for performing run-to-run control of trench profiles. At least one semiconductor wafer is processed. A trench metrology data from the processed semiconductor wafer is acquired. Data relating to at least one process chamber characteristic is acquired while processing the semiconductor wafer. A chamber characteristic adjustment process is performed in response to the trench metrology data and the data relating to the processing chamber characteristic. A feedback adjustment of the processing chamber characteristic is performed in response to the chamber characteristic adjustment process.

Abstract: Various methods of fabricating a conductor structure are provided. In one aspect, a method of fabricating a conductor structure on a first workpiece is provided. A silicon film is formed on the first workpiece. An anti-reflective coating is formed on the silicon film. A mask is formed on a first portion of the anti-reflective coating, while a second portion thereof is left unmasked. The second portion of the anti-reflective coating and the silicon film are etched. The mask is removed, and the anti-reflective coating is removed by isotropic plasma etching. Use of isotropic etching for anti-reflective coating removal eliminates thermal shock associated with heated acid bath anti-reflective coating removal.

Abstract: The present invention provides for a method and an apparatus for controlling critical dimensions. At least one run of semiconductor devices is processed. A critical dimension measurement is performed upon at least one of the processed semiconductor device. An analysis of the critical dimension measurement is performed. A secondary process upon the semiconductor device in response to the critical dimension analysis is performed.

Abstract: A photolithography test structure is provided for measuring the amount of notching associated with photolithography processing. The test structure includes a curved insulating structure placed in close spaced proximity with a conductive, interconnect structure. A pair of conductive pads are deposited at opposite ends of the interconnect structure for measuring the resistance through the interconnect. Depending upon the amount of notching associated with the interconnect, resistance readings will vary. Test areas containing notched interconnect can be compared with controlled areas specifically designed not to have notching in order to determine relative changes in resistance, and to correlate that resistance with notching magnitude. The insulating structure, interconnect structure and conductive pads are processed upon the same substrate material containing the resulting product requiring testing.

Abstract: A photolithography test structure is provided for measuring the amount of notching associated with photolithography processing. The test structure includes a curved insulating structure placed in close spaced proximity with a conductive, interconnect structure. A pair of conductive pads are deposited at opposite ends of the interconnect structure for measuring the resistance through the interconnect. Depending upon the amount of notching associated with the interconnect, resistance readings will vary. Test areas containing notched interconnect can be compared with controlled areas specifically designed not to have notching in order to determine relative changes in resistance, and to correlate that resistance with notching magnitude. The insulating structure, interconnect structure and conductive pads are processed upon the same substrate material containing the resulting product requiring testing.