Abstract: The invention relates generally to an apparatus and method that enables a very accurate initial setup of the coating gap for slot die coater and subsequent control of the coating gap during coating operations such that web splices and web defects do not interrupt the coating process. An highly accurate initial set up is achieved via the use of a tapered or wedge-shaped adjustment member mounted perpendicular to the axis of travel of the coating head where the movement of this tapered or wedge-shaped adjustment member in a direction perpendicular to the axis of travel of the slot die housing adjusts the coating gap in increments on the order of ten microns.

Abstract: The invention relates generally to an apparatus and method that enables a very accurate initial setup of the coating gap for slot die coater and subsequent control of the coating gap during coating operations such that web splices and web defects do not interrupt the coating process. An highly accurate initial set up is achieved via the use of a tapered or wedge-shaped adjustment member mounted perpendicular to the axis of travel of the coating head where the movement of this tapered or wedge-shaped adjustment member in a direction perpendicular to the axis of travel of the slot die housing adjusts the coating gap in increments on the order of ten microns.

Abstract: The invention relates generally to an apparatus and method that enables a very accurate initial setup of the coating gap for slot die coater and subsequent control of the coating gap during coating operations such that web splices and web defects do not interrupt the coating process. An highly accurate initial set up is achieved via the use of a tapered or wedge-shaped adjustment member mounted perpendicular to the axis of travel of the coating head where the movement of this tapered or wedge-shaped adjustment member in a direction perpendicular to the axis of travel of the slot die housing adjusts the coating gap in increments on the order of ten microns.

Abstract: A replaceable gauging element assembly includes a series of gauge modules mounted in spaced series along a gauge bar. The gauge modules each include an upper section having a front face, an intermediate section and a lower section. A series of slots are formed in the front face of the gauge modules for receiving a series of gauge parts therein, with the gauge parts releasably secured within the modules by one or more fasteners. Access openings are formed in the modules for facilitating removal of broken gauge parts from the slots.

Abstract: A single-instruction multiple-data (SIMD) array processor providing enhanced data transfer efficiency. The SIMD array processor includes at least one memory and a plurality of mesh-connected processing elements configured in an array. Each processing element in the array includes at least one “narrow” memory buffer, at least one “wide” data register, and at least one “wide” communication register. The narrow memory buffer is adapted to transfer data serially between the memory and the wide data register, the wide data register is adapted to transfer data directly to the wide communication register, and the wide communication register is adapted to transfer data directly to the communication register of a neighboring processing element while the memory buffer is accessing data from the memory.

Abstract: An SIMD array processor having a scalable and flexible architecture. The SIMD array architecture includes an array of processing elements, a plurality of processor controllers, and at least one other computer system. A system area network interconnects at least one user computer with the processor controllers and the computer system; and, a storage area network interconnects at least one storage device with the processor controllers and the computer system. The SIMD array architecture is adapted to allow different user computers to use different portions of the array of processing elements and/or different processor controllers and computer systems simultaneously. The array of processing elements has a hierarchical structure comprising backplanes, PCB's, ASIC's, and arrays of processing elements. The SIMD array architecture can be scaled by increasing the quantity of backplanes, PCB's, ASIC's, and/or by increasing the size of the arrays of processing elements.

Abstract: A single-instruction multiple-data (SIMD) array processor for processing multi-dimensional node meshes that are either elongated or not elongated in at least one coordinate direction. The SIMD array processor includes a plurality of processor arrays interconnected to form an N-dimensional array. Each processor array in the N-dimensional array is connected to 2N data I/O paths for communicating with 2N processor arrays in the N-dimensional array. Each processor array conceptually located at an interior point of the N-dimensional array is connected to 2N dimensionally adjacent processor arrays in the N-dimensional array. Each processor array conceptually located at one of at least one pair of dimensionally opposite boundaries of the N-dimensional array is connected to fewer than 2N dimensionally adjacent processor arrays and at least one processor array conceptually located at the dimensionally opposing boundary.

Abstract: A parallel processing system including a virtual processing instruction and address generator, for generating processor cell instructions to a parallel processing array such as a multi-dimensional processor array which may have fewer processor cells than the number of nodes in the problem space. The system partitions the memory of each physical processor cell into several equal sections, each section being associated with one node of the problem space. The instruction generator then produces a sequence of processor cell instructions for each node of the given problem space, with appropriate address modifications for each sequence of instructions provided by an address relocation circuit.

Abstract: A multi-dimensional processor cell and processor array with massively parallel input/output includes a processor array having a plurality of processor cells interconnected to form an N-dimensional array. The system includes a first group of processor cells having 2N dimensionally adjacent processor cells. At least one input/output device is connected to a surplus data signal port of a second group of processor cells each having fewer than 2N dimensionally adjacent processor cells, for providing massively parallel input/output between the multi-dimensional processor array and the input/output device. The processor system also includes a front end processor for providing processor array instructions in response to application programs running on the front end processor. A processor cell controller, responsive to the processor array commands, broadcasts a sequence of processor cell instructions to all of the processor cells of the multi-dimensional processor array.

Abstract: A reconfigurable multi-dimensional processor array for processing multi-dimensionally structured data includes a plurality of processor cells arranged in N dimensions and having a plurality of N-1 dimensional processor subarrays. Each of the processor cells has 2N data signal ports operative for forming data signal paths for transmitting and receiving data to and from 2N adjacent processor cells or data communication devices. Each of the N-1 dimensional processor subarrays includes a selected group of processor cells coupled to fewer than 2N other processor cells or data communications devices. Each of the selected group of processor cells includes at least one uncoupled data signal port.