Abstract: A system for equal utilization of blocks of flash memory whereby a processor using algorithmic software functions to sort the usage-value of each block of flash memory so that the system will select the least-used memory block for the next cycle of memory usage. The described system provides direct and immediate access of flash memory to the microprocessor without any intermediate modules or vias which would delay that access. Further, a minimal amount of overhead header information is only required for each flash memory block thus allowing greater areas of memory usage for instructional code data.

Abstract: Control signals are provided for data transfer timing compatibility between two systems or two modules which are not synchronous with each other. Specialized circuitry is provided to ensure timing compatibility in that control signals, transmitted from one system to the other, are handled by interface circuitry which directly transmits the front-end transition and delays the back-end transition so it can be synchronized to the receiving systems clock.

Abstract: In a system of multiple digital modules which is operated synchronously via common clock means, there is provided circuitry for halting each module at the same simultaneously clock-moment after sensing of a selected condition in any one of the digital modules.

Abstract: An expandable memory structure, both vertically and laterally, which uses a plurality of uniformly sized and duplicated chips which includes parity check functionality using an auxiliary parity memory chip of the same type and size. Selection circuitry permits choice of format for odd or even parity.

Abstract: A width-expansible ROM/PROM memory structure includes a plurality of duplicate-type ROM/PROM data memory chips and includes a duplicate-type ROM/PROM parity memory chip. Stored data words of "n" bits can be stored in the memory chips and combined in output to provide a data output word of k.times.n data bits to provide an expanded output data word, where k is the number of data memory chips. Selection means are provided to operate with either an odd parity format or an even parity format.

Abstract: A ROM/PROM memory system circuit structure provides for vertical expansion of data words while providing for enablement of parity checking by the addition of a single auxiliary ROM/PROM memory chip which duplicates the type and size of data memory chips. Additionally, selection means is provided to choose either an odd parity or an even parity format.

Abstract: A power network control system has a plurality of digital modules interconnected. A master logic unit in the network communicates with a specialized protocol to slave logic units in each module. The slave logic unit can instruct a power control circuit to turn-off or turn-on various power supply modules in addition to adjusting a power module in steps of plus or minus fixed percentage amounts.

Abstract: A system for controlling communication in a network of digital modules where each digital module has a maintenance processor which connects the digital module through a network bus to every other digital module's maintenance processor. Each transmitting module can lock up the network bus temporarily for data transmission operations to a specifically addressed receiver module. This system basically permits free communication access of any digital module to any other digital module.

Abstract: A power network control system has a plurality of digital modules interconnected. A master logic unit in the network communicates with a specialized protocol to slave logic units in each module to provide a reliable power control system for selectively (or generally) instructing modules to turn on or to turn off the local power source.