Abstract: A method for generating a superset pinout for a family of devices. First, a pinlist is defined for each device within the family of devices. Second, a superset listing of pins is generated from the pinlist. Third, the superset pinout for the family of devices is created from said superset listing of pins to eliminate potential footprint variations within the family of devices. Fourth, each pin of the superset pinout associated with each member of the family of devices is marked.

Abstract: A method for interconnecting a plurality of dies. The method generally includes receiving a plurality of interconnect requirements for the dies. The interconnect requirements may include a priority for each of a plurality of nets. A position and an angle for one of the dies relative to a substrate may be calculated in response to the interconnect requirements. A plurality of nets may then be routed among the dies and a plurality of substrate pads defining external connections for the substrate. The dies may be mounted to the substrate after routing has been finalized.

Abstract: A semiconductor device that includes an integrated circuit and an HBM structure formed on different semiconductor substrates is provided. The HBM structure may include input or output or input/output circuitry coupled to the integrated circuit and protection structures coupled to the input or output or input/output circuitry. In an embodiment, the integrated circuit may include input or output or input/output structures spaced across an area of the integrated circuit. The input or output or input/output circuitry of the HBM structure may be coupled to the input or output or input/output structures of the integrated circuit. A method for developing a design for an HBM structure is also provided. The method may include coupling an HBM structure formed on a first semiconductor substrate to an integrated circuit formed on a second semiconductor substrate. The method may also include testing the HBM structure and altering the HBM design based on the testing.

Abstract: A ball grid array (BGA) package is disclosed. An interconnect structure is formed on a substrate that electrically connects the electrical device to be housed in the BGA package to the solder balls thereon. Contact pads are formed over the top surface of the substrate. These contact pads electrically connect to the interconnect structure. A layer of solder mask is formed over the substrate that includes openings that overlie the contact pads. The BGA is then completed using conventional process steps. Thereby, a BGA package is formed that includes contact pads disposed such that the contact pads are accessible from the top of the BGA package, making these contact pads easily accessible. Thus, when the BGA is attached to a circuit board, connection to circuits of the electrical device is obtainable.

Abstract: A method for creating pinouts for inter-die connections comprising the steps of filling a number of columns of a computer readable file with information about pads and balls of the inter-die connections, marking portions of the computer readable file indicating a correlation between the pads and the balls, and generating a netlist according to one or more sets of computer executable instructions in the computer readable file.

Abstract: An embodiment of the present invention provides a method and apparatus that effectuates a direct functional interface directly with individual constituent subcomponents of the internal die component, or with particular circuit nodes or conductive trace locales of the surface mount package, without high frequency signal degradation or other electrical problems. An embodiment of the present invention also provides a method and apparatus that effectuates testing access, directly to the internal die component of the surface mount package or to a particular circuit node or conductive trace locale of the surface mount package, enabling performance evaluation and system debugging. Further, an embodiment of the present invention provides a method and apparatus that effectuates integration of surface mount package with an opto-electronic package. Further still, an embodiment of the present invention provides a method and apparatus that achieves these advantages with minimal cost.

Abstract: An apparatus and method integrates optical transceivers for transfer of signals between optical and electronic media with surface mount packages, such as ball grid arrays and quad flat packs. A surface mount package is positioned directly beneath a modular optical transceiver. The surface mount package provides for electrically coupling external signals to the optical transceiver, so as to allow full performance functionality of data transfer components. An electrical coupling mechanism with high performance at high frequency is positioned between the surface mount package and the optical transceiver, electrically connecting them. In one implementation, the optical transceiver module is mounted directly to said surface mount package such that it is removable. In one embodiment, heat dissipation is provided by integral components and thermal vias, in addition to heat sinks.