Patents by Inventor James H. Stathis
James H. Stathis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10746782Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.Type: GrantFiled: November 6, 2017Date of Patent: August 18, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert, James H. Stathis
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Patent number: 10739397Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.Type: GrantFiled: May 10, 2017Date of Patent: August 11, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert, James H. Stathis
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Patent number: 10574240Abstract: An electronic apparatus for testing an integrated circuit (IC) that includes a ring oscillator is provided. The apparatus configures the ring oscillator to produce oscillation at a first frequency and configures the ring oscillator to produce oscillation at a second frequency. The apparatus then compares the second frequency with an integer multiple of the first frequency to determine a resistive voltage drop between a voltage applied to the IC and a local voltage at the ring oscillator. The ring oscillator has a chain of inverting elements forming a long ring and a short ring. The ring oscillator also has an oscillation selection circuit that is configured to disable the short ring so that the ring oscillator produces a fundamental oscillation based on signal propagation through the long ring and enable the short ring so that the ring oscillator produces a harmonic oscillation based on a signal propagation through the short ring and the long ring.Type: GrantFiled: February 28, 2017Date of Patent: February 25, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Keith A. Jenkins, Peilin Song, James H. Stathis, Franco Stellari
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Patent number: 10552278Abstract: A method and system are provided for chip testing. The method includes selectively deploying a chip for future use or discarding the chip to prevent the future use, responsive to a stress history of the chip determined using a non-destructive test procedure. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto. The test procedure further includes ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks. The test procedure also includes calculating a sum by summing the plurality of pattern ranks. The sum calculated during an initial performance of the test procedure is designated as a baseline, and the sum calculated during a subsequent performance of the test procedure is compared to a threshold derived from the baseline to determine the stress history of the chip.Type: GrantFiled: July 13, 2018Date of Patent: February 4, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Keith A. Jenkins, Barry P. Linder, Emily A. Ray, Raphael P. Robertazzi, Peilin Song, James H. Stathis, Kevin G. Stawiasz, Franco Stellari, Alan J. Weger, Emmanuel Yashchin
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Publication number: 20180328977Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.Type: ApplicationFiled: May 10, 2017Publication date: November 15, 2018Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert, James H. Stathis
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Publication number: 20180328979Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.Type: ApplicationFiled: November 6, 2017Publication date: November 15, 2018Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert, James H. Stathis
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Publication number: 20180322025Abstract: A method and system are provided for chip testing. The method includes selectively deploying a chip for future use or discarding the chip to prevent the future use, responsive to a stress history of the chip determined using a non-destructive test procedure. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto. The test procedure further includes ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks. The test procedure also includes calculating a sum by summing the plurality of pattern ranks. The sum calculated during an initial performance of the test procedure is designated as a baseline, and the sum calculated during a subsequent performance of the test procedure is compared to a threshold derived from the baseline to determine the stress history of the chip.Type: ApplicationFiled: July 13, 2018Publication date: November 8, 2018Inventors: Keith A. Jenkins, Barry P. Linder, Emily A. Ray, Raphael P. Robertazzi, Peilin Song, James H. Stathis, Kevin G. Stawiasz, Franco Stellari, Alan J. Weger, Emmanuel Yashchin
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Patent number: 10102090Abstract: A method and system are provided for chip testing. The method includes ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip. The method further includes repeating the test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each pattern based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the pattern ranks. The sum calculated by the ascertaining step is designated as the baseline, and the sum calculated by the repeating step is compared to the threshold to determine the stress history of the chip under test.Type: GrantFiled: May 16, 2016Date of Patent: October 16, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Keith A. Jenkins, Barry P. Linder, Emily A. Ray, Raphael P. Robertazzi, Peilin Song, James H. Stathis, Kevin G. Stawiasz, Franco Stellari, Alan J. Weger, Emmanuel Yashchin
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Patent number: 10103060Abstract: Methods and test structures for testing the reliability of a dielectric material. The test structure may include a first row of contacts and a line comprised of a conductor. The line is laterally spaced in a direction at a minimum distance from the first row of contacts. The test structure further includes a second row of contacts laterally spaced in the direction from the first row of contacts by a distance equal to two times a minimum pitch. The line is laterally positioned between the first row of contacts and the second row of contacts.Type: GrantFiled: June 18, 2015Date of Patent: October 16, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: David G. Brochu, Jr., Roger A. Dufresne, Baozhen Li, Barry P. Linder, James H. Stathis, Ernest Y. Wu
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Publication number: 20180248555Abstract: An electronic apparatus for testing an integrated circuit (IC) that includes a ring oscillator is provided. The apparatus configures the ring oscillator to produce oscillation at a first frequency and configures the ring oscillator to produce oscillation at a second frequency. The apparatus then compares the second frequency with an integer multiple of the first frequency to determine a resistive voltage drop between a voltage applied to the IC and a local voltage at the ring oscillator. The ring oscillator has a chain of inverting elements forming a long ring and a short ring. The ring oscillator also has an oscillation selection circuit that is configured to disable the short ring so that the ring oscillator produces a fundamental oscillation based on signal propagation through the long ring and enable the short ring so that the ring oscillator produces a harmonic oscillation based on a signal propagation through the short ring and the long ring.Type: ApplicationFiled: February 28, 2017Publication date: August 30, 2018Inventors: Keith A. Jenkins, Peilin Song, James H. Stathis, Franco Stellari
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Publication number: 20170329685Abstract: A method and system are provided for chip testing. The method includes ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip. The method further includes repeating the test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each pattern based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the pattern ranks. The sum calculated by the ascertaining step is designated as the baseline, and the sum calculated by the repeating step is compared to the threshold to determine the stress history of the chip under test.Type: ApplicationFiled: May 16, 2016Publication date: November 16, 2017Inventors: Keith A. Jenkins, Barry P. Linder, Emily A. Ray, Raphael P. Robertazzi, Peilin Song, James H. Stathis, Kevin G. Stawiasz, Franco Stellari, Alan J. Weger, Emmanuel Yashchin
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Publication number: 20160372389Abstract: Methods and test structures for testing the reliability of a dielectric material. The test structure may include a first row of contacts and a line comprised of a conductor. The line is laterally spaced in a direction at a minimum distance from the first row of contacts. The test structure further includes a second row of contacts laterally spaced in the direction from the first row of contacts by a distance equal to two times a minimum pitch. The line is laterally positioned between the first row of contacts and the second row of contacts.Type: ApplicationFiled: June 18, 2015Publication date: December 22, 2016Inventors: David G. Brochu, JR., Roger A. Dufresne, Baozhen Li, Barry P. Linder, James H. Stathis, Ernest Y. Wu
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Patent number: 9287185Abstract: Methods and systems determine an original statistical variance of an original failure distribution of a component (that is common to all chips tested) that occurs during manufacturing of wafers containing such chips. These methods and systems determine a first statistical variance of a reconstructed failure distribution, relative to sample size; and determine a second statistical variance of a mean time to failure of the component, relative to sample size. The first and second statistical variances are combined into a total reconstruction variance. Methods and systems determine whether the original statistical variance is less than the total reconstruction variance to identify whether the process of creating the reconstructed failure distribution can be used. Therefore, these methods and systems prohibit testing of the additional wafers manufactured using the specific wafer design and manufacturing process when on the original statistical variance is less than the total reconstruction variance.Type: GrantFiled: June 29, 2015Date of Patent: March 15, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Griselda Bonilla, Baozhen Li, Barry P. Linder, James H. Stathis, Ernest Y. Wu, Kai Zhao
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Patent number: 9026981Abstract: Embodiments relate to methods, computer systems and computer program products for performing a dielectric reliability assessment for an advanced semiconductor. Embodiments include receiving data associated with a test of a macro of the advanced semiconductor to a point of dielectric breakdown. Embodiments also include scaling the data for the macro down to a reference area and extracting a parameter for a Weibull distribution from the scaled down data for the reference area. Embodiments further include deriving a cluster factor (?) from the scaled down data for the reference area and projecting a failure rate for a larger area of the advanced semiconductor based on the extracted parameter, the cluster factor and the recorded data associated with the dielectric breakdown of the macro.Type: GrantFiled: June 19, 2014Date of Patent: May 5, 2015Assignee: International Business Machines CorporationInventors: Baozhen Li, James H. Stathis, Ernest Y. Wu
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Publication number: 20140351785Abstract: Embodiments relate to methods, computer systems and computer program products for performing a dielectric reliability assessment for an advanced semiconductor. Embodiments include receiving data associated with a test of a macro of the advanced semiconductor to a point of dielectric breakdown. Embodiments also include scaling the data for the macro down to a reference area and extracting a parameter for a Weibull distribution from the scaled down data for the reference area. Embodiments further include deriving a cluster factor (?) from the scaled down data for the reference area and projecting a failure rate for a larger area of the advanced semiconductor based on the extracted parameter, the cluster factor and the recorded data associated with the dielectric breakdown of the macro.Type: ApplicationFiled: June 19, 2014Publication date: November 27, 2014Inventors: BAOZHEN LI, JAMES H. STATHIS, ERNEST Y. WU
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Patent number: 8839180Abstract: Embodiments relate to methods, computer systems and computer program products for performing a dielectric reliability assessment for an advanced semiconductor. Embodiments include receiving data associated with a test of a macro of the advanced semiconductor to a point of dielectric breakdown. Embodiments also include scaling the data for the macro down to a reference area and extracting a parameter for a Weibull distribution from the scaled down data for the reference area. Embodiments further include deriving a cluster factor (?) from the scaled down data for the reference area and projecting a failure rate for a larger area of the advanced semiconductor based on the extracted parameter, the cluster factor and the recorded data associated with the dielectric breakdown of the macro.Type: GrantFiled: May 22, 2013Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Baozhen Li, James H. Stathis, Ernest Y. Wu
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Patent number: 6602772Abstract: An apparatus and method for evaluating the performance of a test dielectric material for use as a gate dielectric. The method comprises exposing a coated layer of the dielectric to a concentration of atomic hydrogen. The method may comprise (a) measuring an initial value of interface-state density in the test dielectric, (b) exposing the coated test dielectric to a concentration of atomic hydrogen in a remote plasma, and then (c) measuring a post-exposure value of interface-state density in the test dielectric. Steps (b) and (c) may be repeated with incrementally higher concentrations of atomic hydrogen to determine a rate of change in interface-state density value as a function of atomic hydrogen concentration, which may then be related to the projected charge-to-breakdown or time-to-breakdown of the test dielectric layer when the dielectric is used as the gate dielectric.Type: GrantFiled: December 4, 2001Date of Patent: August 5, 2003Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, Eduard A. Cartier, James H. Stathis
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Publication number: 20020070675Abstract: An apparatus and method for evaluating the performance of a test dielectric material for use as a gate dielectric. The method comprises exposing a coated layer of the dielectric to a concentration of atomic hydrogen. The method may comprise (a) measuring an initial value of interface-state density in the test dielectric, (b) exposing the coated test dielectric to a concentration of atomic hydrogen in a remote plasma, and then (c) measuring a post-exposure value of interface-state density in the test dielectric. Steps (b) and (c) may be repeated with incrementally higher concentrations of atomic hydrogen to determine a rate of change in interface-state density value as a function of atomic hydrogen concentration, which may then be related to the projected charge-to-breakdown or time-to-breakdown of the test dielectric layer when the dielectric is used as the gate dielectric.Type: ApplicationFiled: December 4, 2001Publication date: June 13, 2002Inventors: Wagdi W. Abadeer, Eduard A. Cartier, James H. Stathis
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Patent number: 6326732Abstract: An apparatus and method for evaluating the performance of a test dielectric material for use as a gate dielectric. The method comprises exposing a coated layer of the dielectric to a concentration of atomic hydrogen. The method may comprise (a) measuring an initial value of interface-state density in the test dielectric, (b) exposing the coated test dielectric to a concentration of atomic hydrogen in a remote plasma, and then (c) measuring a post-exposure value of interface-state density in the test dielectric. Steps (b) and (c) may be repeated with incrementally higher concentrations of atomic hydrogen to determine a rate of change in interface-state density value as a function of atomic hydrogen concentration, which may then be related to the projected charge-to-breakdown or time-to-breakdown of the test dielectric layer when the dielectric is used as the gate dielectric.Type: GrantFiled: February 16, 1999Date of Patent: December 4, 2001Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, Eduard A. Cartier, James H. Stathis