Abstract: Example methods and apparatus to detect data dependencies in an instruction pipeline are disclosed. A disclosed example method uses an address pointer associated with a first instruction and indicates a first data dependency status of the first instruction. The example method then indicates a second data dependency status of the second instruction based on an instruction type of the first instruction and an instruction type of a second instruction.

Abstract: A method of instruction issue (3200) in a microprocessor (1100, 1400, or 1500) with execution pipestages (E1, E2, etc.) and that executes a producer instruction Ip and issues a candidate instruction I0 (3245) having a source operand dependency on a destination operand of instruction Ip. The method includes issuing the candidate instruction I0 as a function (1720, 1950, 1958, 3235) of a pipestage EN(I0) of first need by the candidate instruction for the source operand, a pipestage EA(Ip) of first availability of the destination operand from the producer instruction, and the one execution pipestage E(Ip) currently associated with the producer instruction. A method of data forwarding (3300) in a microprocessor (1100, 1400, or 1500) having a pipeline (1640) having pipestages (E1, E2, etc.

Abstract: A cache memory that completes an in-flight operation with another cache that collides with a snoop operation, rather than canceling the in-flight operation. Operations to the cache comprise a query pass and one or more finish passes. When the cache detects a snoop query intervening between the query pass and a finish pass of the in-flight operation, the cache generates a more up-to-date status for the snoop query that takes into account the tag status to which the in-flight finish pass will update the implicated cache line. This is necessary because otherwise the snoop query might not see the affect of the in-flight finish pass status update. This allows the in-flight finish pass to complete instead of being cancelled and the snoop finish pass to correctly update the status after the in-flight finish pass, and to provide modified data from the cache line to the externally snooped transaction.

Abstract: An associative cache memory having an integrated tag and LRU array storing pseudo-LRU information on a per way basis, obviating the need for a separate LRU array storing pseudo-LRU information on a per row basis. Each way of the integrated array stores decoded bits of pseudo-LRU information along with a tag. An encoder reads the decoded bits from all the ways of the selected row and encodes the decoded bits into standard pseudo-LRU form. The control logic selects a replacement way based on the encoded pseudo-LRU bits. The control logic then generates new decoded pseudo-LRU bits and updates only the replacement way of the selected row with the new decoded pseudo-LRU bits. Thus, the control logic individually updates only the decoded bits of the replacement way concurrent with the tag of the replacement way, without requiring update of the decoded bits in the non-replacement ways of the row.