Patents by Inventor James Hartfiel Comfort

James Hartfiel Comfort has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Vertical transport MOSFETs and method for making the same
    Publication number: 20010017392
    Abstract: MOSFET comprising:
    Type: Application
    Filed: March 22, 2001
    Publication date: August 30, 2001
    Applicant: International Business Machines Corporation.
    Inventors: James Hartfiel Comfort, Young Hoon Lee, Yaun Taur, Samuel Jonas Wind, Hom-Sum Philip Wong
  • Structure and fabrication method for non-planar memory elements
    Patent number: 6242321
    Abstract: Structures for memory cell applications, including capacitors for DRAM and ferroelectric memory cells from FRAM, whose method of manufacture consists of depositing a ferroelectric or high-epsilon dielectric material to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In the preferred embodiment, the cavity into which the dielectric is deposited is defined by the gap between the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the dielectric deposition.
    Type: Grant
    Filed: May 3, 1999
    Date of Patent: June 5, 2001
    Assignee: International Business Machines Corporation
    Inventors: Raul Edmundo Acosta, James Hartfiel Comfort, Alfred Grill, David Edward Kotecki, Katherine Lynn Saenger
  • Plating of noble metal electrodes for DRAM and FRAM
    Patent number: 5789320
    Abstract: Noble metal plating on a preexisting seed layer is used in the fabrication of electrodes for DRAM and FRAM. The plating may be spatially selective or nonselective. In the nonselective case, a blanket film is first plated and then patterned after deposition by spatially selective material removal. In the selective case, the plated deposits are either selectively grown in lithographically defined areas by a through-mask plating technique, or selectively grown as a conformal coating on the exposed regions of a preexisting electrode structure. A diamond-like carbon mask can be used in the plating process. A self-aligned process is disclosed for selectively coating insulators in a through-mask process.
    Type: Grant
    Filed: April 23, 1996
    Date of Patent: August 4, 1998
    Assignee: International Business Machines Corporation
    Inventors: Panayotis Constantinou Andricacos, James Hartfiel Comfort, Alfred Grill, David Edward Kotecki, Vishnubhai Vitthalbhai Patel, Katherine Lynn Saenger, Alejandro Gabriel Schrott
  • Structure and fabrication method for non-planar memory elements
    Patent number: 5757612
    Abstract: Structures for memory cell applications, including capacitors for DRAM and ferroelectric memory cells from FRAM, whose method of manufacture consists of depositing a ferroelectric or high-epsilon dielectric material to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In the preferred embodiment, the cavity into which the dielectric is deposited is defined by the gap between the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the dielectric deposition.
    Type: Grant
    Filed: April 23, 1996
    Date of Patent: May 26, 1998
    Assignee: International Business Machines Corporation
    Inventors: Raul Edmundo Acosta, James Hartfiel Comfort, Alfred Grill, David Edward Kotecki, Katherine Lynn Saenger