Patents by Inventor James HEISLER

James HEISLER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and methods for magnetic mixing
    Patent number: 10851336
    Abstract: Methods and systems for magnetic mixing. Particular embodiments relate to applying a magnetic field to move a magnetically responsive component in a chamber.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: December 1, 2020
    Assignee: LUMINEX CORPORATION
    Inventors: Doug Whitman, James Heisler, Colin Bozarth, Germaine Siew, Charles Collins, Eric Smith
  • APPARATUS AND METHODS FOR MAGNETIC MIXING
    Publication number: 20190093061
    Abstract: Methods and systems for magnetic mixing. Particular embodiments relate to applying a magnetic field to move a magnetically responsive component in a chamber.
    Type: Application
    Filed: November 28, 2018
    Publication date: March 28, 2019
    Applicant: LUMINEX CORPORATION
    Inventors: Doug WHITMAN, James HEISLER, Colin BOZARTH, Germaine SIEW, Charles COLLINS, Eric SMITH
  • Apparatus and methods for magnetic mixing
    Patent number: 10179899
    Abstract: Methods and systems for magnetic mixing. Particular embodiments relate to applying a magnetic field to move a magnetically responsive component in a chamber.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: January 15, 2019
    Assignee: LUMINEX CORPORATION
    Inventors: Doug Whitman, James Heisler, Colin Bozarth, Germaine Siew, Charles Collins, Eric Smith
  • APPARATUS AND METHODS FOR MAGNETIC MIXING
    Publication number: 20150368601
    Abstract: Methods and systems for magnetic mixing. Particular embodiments relate to applying a magnetic field to move a magnetically responsive component in a chamber.
    Type: Application
    Filed: June 5, 2015
    Publication date: December 24, 2015
    Applicant: LUMINEX CORPORATION
    Inventors: Doug WHITMAN, James HEISLER, Colin BOZARTH, Germaine SIEW, Charles COLLINS, Eric SMITH
  • EDRAM having a dynamically-sized cache memory and associated method
    Patent number: 5983313
    Abstract: The method and apparatus of the current invention relates to an intelligent cache management system for servicing a main memory and a cache. The cache resources are allocated to segments of main memory rows based on a simple or complex allocation process. The complex allocation performs a predictive function allocating scarce resources based on the probability of future use. The apparatus comprises a main memory coupled by a steering unit to a cache. The steering unit controls where in cache a given main memory row segment will be placed. The operation of the steering unit is controlled by an intelligent cache allocation unit. The unit allocates new memory access requests cache locations which are least frequently utilized. Since a given row segment may be placed anywhere in a cache row, the allocation unit performs the additional function of adjusting the column portion of a memory access request to compensate for the placement of the requested segment in the cache.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: November 9, 1999
    Assignee: Ramtron International Corporation
    Inventors: Doyle James Heisler, James Dean Joseph, Dion Nickolas Heisler
  • EDRAM with integrated generation and control of write enable and column latch signals and method for making same
    Patent number: 5835442
    Abstract: An EDRAM device includes an EDRAM memory array on a semiconductor chip. A row enable signal generator and a column address latch signal generator are provided on the same semiconductor chip for generating row enable and column address latch signals for application to the EDRAM memory array.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: November 10, 1998
    Assignee: Enhanced Memory Systems, Inc.
    Inventors: James Dean Joseph, Dion Nickolas Heisler, Doyle James Heisler
  • Multibus cached memory system
    Patent number: 5802560
    Abstract: A method and apparatus for use in computer systems utilizes a memory chip employing multiple distributed SRAM caches directly linked to a single DRAM main memory block. Each cache is directly linked to a different bus. Each chip further contains a partially distributed arbitration and control circuit for implementing cache policy and arbitrating memory refresh cycles.
    Type: Grant
    Filed: August 30, 1995
    Date of Patent: September 1, 1998
    Assignee: Ramton International Corporation
    Inventors: James Dean Joseph, Doyle James Heisler, Dion Nickolas Heisler