Abstract: A computer network serviced by a maintenance subsystem holds a control processing module (CPM) holding a Data Path Array as interface to a main memory module and I/O Module. A maintenance controller in the CPM has a preloaded Flash Memory unit holding all the necessary operating addresses and data which can be rapidly transferred via a special wide parallel high speed data bus to a data path array unit for subsequent conveyance to a channel microcode block in a main memory module. The operating data include channel microcode data necessary for the I/O Module to communicate with different types of peripheral devices.

Abstract: A central processing module (CPM) uses a data path array interface connecting dual system busses to a main memory module and I/O module. A maintenance controller in the CPM manages a programmable array logic unit controller to read out microcode words in the main memory module to verify their accuracy by comparison with an original data base of microcode words in a flash memory which was earlier pre-loaded from a maintenance subsystem. A high speed auxiliary data bus controlled by the programmable array logic controller, provides a high speed transfer channel for moving the main memory words to the maintenance controller which can then institute a verification procedure for each memory word.

Abstract: A computer network having a Control Processing Module (CPM) maintained by an external Maintenance Subsystem where the CPM has JTAG compatible digital units, but where the Cache Module is not JTAG compatible. Specialized transceivers having Boundary Scan Registers are activated to enable loading of address words in a Tag RAM while concomitantly placing correct initial parity data in a Parity RAM without need to continue communication with the external Maintenance Subsystem. The Boundary Scan Registers in said transceivers are set up to perform as up-counters to sequence through all address locations in the Tag RAM while a Control PAL calculates and places the associated parity values in each corresponding address location in the Parity RAM.

Abstract: A network comprising a central processing module and maintenance subsystem which provides a system for rapid loading of instruction words in a microcode RAM whereby microcode instruction words from the maintenance subsystem are preliminarily loaded into a flash memory in the central processing module. A maintenance controller transfers the microcode instruction words from the flash memory over a transfer bus to a data path array which connects to a processor-instruction memory bus for enabling microcode addresses and data words to be rapidly transferred into a microcode RAM instruction memory. A programmable controller activated by the maintenance controller in the central processing module then regulates the transfer of data to the microcode RAM by providing incrementation of the addresses of the instruction words on an automatic basis and thus relieving the processor of this function.

Abstract: A system and method for using standard JTAG protocol for testing protocol compliant and non-protocol compliant digital devices without altering the JTAG protocol or the non-compliant device. A specialized Test Access Port Controller controls and monitors the states applied to the non-compliant device in order to eliminate the PAUSE state in the non-compliant device and to limit the Run-Test/Idle state to one clock period.

Abstract: A digital system which normally initializes and tests non-JTAG logic units is adapted to test JTAG protocol compatible logic units. A JTAG translator unit provides an instruction control register and a Data Register. The Control Register has control bits for selecting Test-Mode-Select and Test Clock signals for the JTAG compatible units and Shift/Hold signals for the non-JTAG compatible logic units. The Data Register supplies diagnostic test bits to registers in both the JTAG and non-JTAG logic units. Additionally, the Control Register can initiate automatic incrementation of addresses to a control state RAM for rapid loading of microcode.

Abstract: A system whereby a microcode RAM in a central processing module can have each microcode word rapidly accessed and transferred to a maintenance controller to compare each accessed microcode word with a corresponding microcode word in a set of microcode words which were pre-loaded in a flash memory.