Abstract: A method of and an apparatus for conditionally bypassing the error correction function of a large scale integrated (LSI) semiconductor random access memory (RAM) is disclosed. A content addressable memory (CAM) is utilized to store the addresses of the addressable locations in the RAM in which an error was previously detected, and on each memory reference both the CAM and the RAM are simultaneously referenced by the same address. Upon a memory reference, the read data from, i.e., the date read out of, the RAM is concurrently coupled directly to an Interface Register and directly to the error detection and correction circuitry (ECC) and thence to the Interface Register. If the CAM does not contain the address, the read data that is coupled to the Interface Register is gated out at a first relatively early gate pulse. However, if the CAM does contain the address, the corrected read data from the ECC is then gated out of the Interface Register at a second relatively later gate pulse.

Abstract: An apparatus for and a method of providing error correction of the address word of a cache memory system (CMS) utilizing post-write storage of the least recently used (LRU) block of data words. Error correction circuitry (ECC) is provided at the output of the address buffer (CAB) portion of the cache memory system so that the address word that specifies the addressable location in the main storage unit (MSU) into which the block of data words, which block of data words is stored in the data buffer (CDB) portion of the cache memory, is to be stored or written-back is error corrected upon readout. This error correction of the address word ensures that correctable errors in the address buffer provided address words do not generate a Miss signal by the storage interface unit (SIU) which, in turn, requires a MSU reference even though the desired address word and the associated data word are available in the cache memory system.

Abstract: A method of and an apparatus for performing, in a Cache memory system, the Priority determination of what Requestor, of R Requestors, is to be granted priority by the Priority Network while simultaneously comparing, in parallel, all of the R Requestors' addresses for a Match condition in R Cache memories. The Cache memory system incorporates a separate Cache memory or associative memory for each Requestor, each of which Cache memories is comprised of an Address Buffer or Search memory, in which the associated Requestors' addresses are stored, and a Data Buffer or Associated memory, in which the data that are associated with each of the Requestors' addresses are stored. Thus, while the Priority Request signals from all of the requesting Requestors are being coupled to the single Priority Network, each of the requesting Requestors' addresses is coupled to each of the requesting Requestor separately associated Cache memory.