Patents by Inventor James Hippisley Robinson
James Hippisley Robinson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230237325Abstract: Techniques for mixed-precision data manipulation for neural network data computation are disclosed. A first left group comprising eight bytes of data and a first right group of eight bytes of data are obtained for computation using a processor. A second left group comprising eight bytes of data and a second right group of eight bytes of data are obtained. A sum of products is performed between the first left and right groups and the second left and right groups. The sum of products is performed on bytes of 8-bit integer data. A first result is based on a summation of eight values that are products of the first group’s left eight bytes and the second group’s left eight bytes. A second result is based on the summation of eight values that are products of the first group’s left eight bytes and the second group’s right eight bytes. Results are output.Type: ApplicationFiled: February 24, 2023Publication date: July 27, 2023Inventors: James Hippisley Robinson, Sanjay Patel
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Patent number: 11615307Abstract: Techniques for mixed-precision data manipulation for neural network data computation are disclosed. A first left group comprising eight bytes of data and a first right group of eight bytes of data are obtained for computation using a processor. A second left group comprising eight bytes of data and a second right group of eight bytes of data are obtained. A sum of products is performed between the first left and right groups and the second left and right groups. The sum of products is performed on bytes of 8-bit integer data. A first result is based on a summation of eight values that are products of the first group's left eight bytes and the second group's left eight bytes. A second result is based on the summation of eight values that are products of the first group's left eight bytes and the second group's right eight bytes. Results are output.Type: GrantFiled: August 5, 2020Date of Patent: March 28, 2023Assignee: MIPS Tech, LLCInventors: James Hippisley Robinson, Sanjay Patel
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Publication number: 20210034979Abstract: Techniques for mixed-precision data manipulation for neural network data computation are disclosed. A first left group comprising eight bytes of data and a first right group of eight bytes of data are obtained for computation using a processor. A second left group comprising eight bytes of data and a second right group of eight bytes of data are obtained. A sum of products is performed between the first left and right groups and the second left and right groups. The sum of products is performed on bytes of 8-bit integer data. A first result is based on a summation of eight values that are products of the first group's left eight bytes and the second group's left eight bytes. A second result is based on the summation of eight values that are products of the first group's left eight bytes and the second group's right eight bytes. Results are output.Type: ApplicationFiled: August 5, 2020Publication date: February 4, 2021Inventors: James Hippisley Robinson, Sanjay Patel
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Patent number: 10846089Abstract: A binary logic circuit for manipulating an input binary string includes a first stage of a first group of multiplexers arranged to select respective portions of an input binary string and configured to receive a respective first control. A second stage is included in which a plurality of a second group of multiplexers is arranged to select respective portions of the input binary string and configured to receive a respective second control signal. The control signals are provided such that each multiplexer of a second group is configured to select a respective second portion of the first binary string. Control circuitry is configured to generate the first and second control signals such that two or more of the first groups and/or two or more of the second groups of multiplexers are independently controllable.Type: GrantFiled: August 31, 2018Date of Patent: November 24, 2020Assignee: MIPS Tech, LLCInventors: James Hippisley Robinson, Morgyn Taylor
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Publication number: 20190138308Abstract: A processor is configured to implement an instruction set architecture for accessing data that includes loading data elements from a memory containing data blocks separated by block boundaries. The instruction set architecture includes a first type of data load instruction for loading an aligned data structure from the memory and a second type of data load instruction for loading an unaligned data structure from the memory. The loading includes fetching a data load instruction of the second type and loading from the memory according to the data load instruction of the second type. The resulting data structure formed of n consecutive data elements is determined from the data load instruction. The data structure loaded from memory is formed of n consecutive unaligned data elements. The processor is similarly configured to implement storing data elements from a set of registers to a memory containing data blocks separated by block boundaries.Type: ApplicationFiled: September 14, 2018Publication date: May 9, 2019Inventors: James Hippisley Robinson, Morgyn Taylor, Richard Fuhler, Sanjay Patel
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Publication number: 20190065202Abstract: Instruction set architectures (ISAs) and apparatus and methods related thereto comprise a variable length instruction set that includes one or more pointer-size controlled memory access instructions of a smaller length (e.g. 16 bits) wherein the size of the data accessed by such an instruction is dynamically determined based on the size of the pointer. Specifically, when a pointer-size controlled memory access instruction is received at a decode unit, the decode unit outputs one or more control signals to cause an execution unit to perform a memory access of a first size (e.g. 32 bits) when the pointer size is the first size (e.g. 32 bits), and output one or more control signals to cause the execution unit to perform a memory access of a second size (e.g. 64 bits) when the pointer size is the second size (e.g. 64 bits).Type: ApplicationFiled: August 31, 2018Publication date: February 28, 2019Inventors: James Hippisley Robinson, Morgyn Taylor
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Publication number: 20190065199Abstract: Described herein are instruction set architectures (ISAs), and related data processing apparatuses and methods, with two or more non-contiguous blocks of preserved registers wherein the registers to be saved or restored are identified in a save or restore instruction via a number of registers to be saved/restored (Num_Reg) and a starting register (rStart). Specifically, in the ISAs, apparatuses, and methods described herein, the registers to be saved or restored are identified as the Num_Reg registers in a predetermined sequence starting with rStart wherein, in the predetermined sequence, each register is followed by the next highest numbered register except the highest numbered preserved register, which is followed by the lowest numbered preserved register.Type: ApplicationFiled: August 31, 2018Publication date: February 28, 2019Inventors: James Hippisley Robinson, Morgyn Taylor, Matthew Fortune
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Publication number: 20190065201Abstract: Instruction set architectures (ISAs) and apparatus and methods related thereto comprise an instruction set that includes one or more instructions which identify the global pointer (GP) register as an operand (e.g., base register or source register) of the instruction. Identification can be implicit. By implicitly identifying the GP register as an operand of the instruction, one or more bits of the instruction that were dedicated to explicitly identifying the operand (e.g., base register or source register) can be used to extend the size of one or more other operands, such as the offset or immediate, to provide longer offsets or immediates.Type: ApplicationFiled: August 31, 2018Publication date: February 28, 2019Inventors: James Hippisley Robinson, Morgyn Taylor, Matthew Fortune, Richard Fuhler, Sanjay Patel
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Publication number: 20190065145Abstract: A binary logic circuit for manipulating an input binary string includes a first stage of a first group of multiplexers arranged to select respective portions of an input binary string and configured to receive a respective first control. A second stage is included in which a plurality of a second group of multiplexers is arranged to select respective portions of the input binary string and configured to receive a respective second control signal. The control signals are provided such that each multiplexer of a second group is configured to select a respective second portion of the first binary string. Control circuitry is configured to generate the first and second control signals such that two or more of the first groups and/or two or more of the second groups of multiplexers are independently controllable.Type: ApplicationFiled: August 31, 2018Publication date: February 28, 2019Inventors: James Hippisley Robinson, Morgyn Taylor
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Publication number: 20130159781Abstract: A method of tracing processor instructions includes forming a compressed trace stream with a dynamic unit width indicator and a value block. The dynamic unit width indicator includes an address/data width indicator qualified by a unit indicator. The unit value block has a width that is a function of the address/data width indicator and the unit indicator.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicant: MIPS TECHNOLOGIES, INC.Inventor: James Hippisley Robinson
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Publication number: 20100312991Abstract: A re-encoded instruction set architecture (ISA) provides smaller bit-width instructions or a combination of smaller and larger bit-width instructions to improve instruction execution efficiency and reduce code footprint. The ISA can be re-encoded from a legacy ISA having larger bit-width instructions, and the re-encoded ISA can maintain assembly-level compatibility with the ISA from which it is derived. In addition, the re-encoded ISA can have new and different types of additional instructions, including instructions with encoded arguments determined by statistical analysis and instructions that have the effect of combinations of instructions.Type: ApplicationFiled: March 26, 2010Publication date: December 9, 2010Applicant: MIPS Technologies, Inc.Inventors: Erik K. NORDEN, James Hippisley Robinson, David Yiu-Man Lau