Patents by Inventor James Holland

James Holland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11232834
    Abstract: Systems, methods, and computer-readable media are provided for providing pose estimation in extended reality systems. An example method can include tracking, in a lower-power processing mode using a set of lower-power circuit elements on an integrated circuit, a position and orientation of a computing device during a lower-power processing period, the set of lower-power circuit elements including a static random-access memory (SRAM); suspending, based on a triggering event, the tracking in the lower-power processing mode; initiating a higher-power processing mode for tracking the position and orientation of the computing device during a higher-power processing period; and tracking, in the higher-power processing mode using a set of higher-power circuit elements on the integrated circuit and a dynamic random-access memory (DRAM), the position and orientation of the computing device during the higher-power processing period.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: January 25, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Wesley James Holland, Mehrad Tavakoli, Injoon Hong, Huang Huang, Simon Peter William Booth, Gerhard Reitmayr
  • Publication number: 20220014740
    Abstract: An example apparatus includes image processing circuitry to determine an uncovered region of a background image in a current video frame relative to the background image in a previous video frame, the uncovered region obscured in the previous video frame by a first foreground region of the previous video frame, and the uncovered region uncovered in the current video frame based on movement of a second foreground region in the current video frame relative to the first foreground region of the previous video frame, and encoder circuitry to generate an updated frame portion by encoding the second foreground region and dirty blocks of the background image corresponding to the uncovered region without encoding static blocks of the background image, the static blocks not corresponding to the uncovered region, and store the updated frame portion in the at least one memory.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Inventors: Stanley Baran, Satish Kumar Bhrugumalla, Kristoffer Fleming, Charu Srivastava, James Holland, Jong Dae Oh
  • Patent number: 11140375
    Abstract: In some aspects, the present disclosure provides a method for sharing a single optical sensor between multiple image processors. In some embodiments, the method includes receiving, at a control arbiter, a first desired configuration of a first one or more desired configurations for capturing an image frame by the optical sensor, the first one or more desired configurations communicated from a primary image processor. The method may also include receiving, at the control arbiter, a second desired configuration of a second one or more desired configurations for capturing the image frame by the optical sensor, the second one or more desired configurations communicated from a secondary image processor. The method may also include determining, by the control arbiter, an actual configuration for capturing the image frame by the optical sensor, the actual configuration based on the first desired configuration and the second desired configuration.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 5, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Wesley James Holland, Satish Goverdhan, Venkata Rajesh Kumar Sastrula, Ramesh Ramaswamy, Songhe Cai, Ling Feng Huang, Chih-Chi Cheng, Huang Huang, Rajakumar Govindaram
  • Publication number: 20210306640
    Abstract: Techniques related to video coding using look ahead analysis and block based back propagation for block level quantization parameters are discussed. Such techniques include adaptively selecting frames subsequent to a target frame in a display order for use in the back propagation, propagating values to blocks of the target frame that are indicative of the importance of the blocks to the encode of the subsequent frames, and encoding the target frame using block level quantization parameters based on the propagated values.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Applicant: Intel Corporation
    Inventors: Jason Tanner, James Holland
  • Publication number: 20210279469
    Abstract: A computing device is configured to determine the provenance of an image. The computing device may receive an image. The computing device may generate an image capture profile associated with the image based at least in part on data generated during an image capture process. The computing device may determine whether the image is an authentic image based at least in part on the image capture profile. The computing device may, in response to determining that the image is an authentic image, generate a digital signature associated with the image.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 9, 2021
    Inventor: Wesley James Holland
  • Patent number: 11106328
    Abstract: Systems, methods, and non-transitory media are provided for generating private control interfaces for extended reality (XR) experiences. An example method can include determining a pose of an XR device within a mapped scene of a physical environment associated with the XR device; detecting a private region in the physical environment and a location of the private region relative to the pose of the XR device, the private region including an area estimated to be within a field of view (FOV) of a user of the XR device and out of a FOV of a person in the physical environment, a recording device in the physical environment, and/or an object in the physical environment; based on the pose of the XR device and the location of the private region, mapping a virtual private control interface to the private region; and rendering the virtual private control interface within the private region.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: August 31, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Wesley James Holland, Ramesh Chandrasekhar, Daniel James Guest, Sebastien Mounier, Bijan Forutanpour
  • Publication number: 20210200679
    Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.
    Type: Application
    Filed: March 17, 2021
    Publication date: July 1, 2021
    Inventors: Andrew Edmund TURNER, George PATSILARAS, Bohuslav RYCHLIK, Wesley James HOLLAND, Jeffrey SHABEL, Simon Peter William BOOTH
  • Patent number: 11049266
    Abstract: An apparatus comprises a processor to divide a first point cloud data set frame representing a three dimensional space at a first point in time into a matrix of blocks, determine at least one three dimensional (3D) motion vector for at least a subset of blocks in the matrix of blocks, generate a predicted second point cloud data set frame representing a prediction of the three dimensional space at a second point in time by applying the at least one 3D motion vector to the subset of blocks in the matrix of blocks, compare the predicted second point cloud data set frame to a second point cloud data set frame representing a prediction of the three dimensional space at a second point in time to generate a prediction error parameter, and encode the second point cloud data set frame as a function of the first point cloud data set frame and the at least one three dimensional (3D) motion vector when the prediction error factor is beneath an error threshold to produce an encoded second point cloud data set frame.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 29, 2021
    Assignee: INTEL CORPORATION
    Inventors: Scott Janus, Barnan Das, Hugues Labbe, Jong Dae Oh, Gokcen Cilingir, James Holland, Narayan Biswal, Yi-Jen Chiu, Qian Xu, Mayuresh Varerkar, Sang-Hee Lee, Stanley Baran, Srikanth Potluri, Jason Ross, Maruthi Sandeep Maddipatla
  • Publication number: 20210195159
    Abstract: In some aspects, the present disclosure provides a method for sharing a single optical sensor between multiple image processors. In some embodiments, the method includes receiving, at a control arbiter, a first desired configuration of a first one or more desired configurations for capturing an image frame by the optical sensor, the first one or more desired configurations communicated from a primary image processor. The method may also include receiving, at the control arbiter, a second desired configuration of a second one or more desired configurations for capturing the image frame by the optical sensor, the second one or more desired configurations communicated from a secondary image processor. The method may also include determining, by the control arbiter, an actual configuration for capturing the image frame by the optical sensor, the actual configuration based on the first desired configuration and the second desired configuration.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Inventors: Wesley James HOLLAND, Satish GOVERDHAN, Venkata Rajesh Kumar SASTRULA, Ramesh RAMASWAMY, Songhe CAI, Ling Feng HUANG, Chih-Chi CHENG, Huang HUANG, Rajakumar GOVINDARAM
  • Publication number: 20210174047
    Abstract: In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.
    Type: Application
    Filed: December 4, 2019
    Publication date: June 10, 2021
    Inventors: Wesley James HOLLAND, Rashmi KULKARNI, Ling Feng HUANG, Huang HUANG, Jeffrey SHABEL, Chih-Chi CHENG, Satish ANAND, Songhe CAI, Simon Peter William BOOTH, Bohuslav RYCHLIK
  • Patent number: 11013726
    Abstract: The present invention includes substituted pyridinone-containing tricyclic compounds, and compositions comprising the same, that can be used to treat or prevent hepatitis B virus (HBV) infection in a patient. In certain embodiments, the compounds and compositions of the invention inhibit and/or reduce HBsAg secretion.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: May 25, 2021
    Assignee: Arbutus Biopharma Corporation
    Inventors: Laurèn Danielle Bailey, Yingzhi Bi, Shuai Chen, Bruce D. Dorsey, Dimitar B. Gotchev, Richard James Holland, Ramesh Kakarla, Duyan Nguyen, Mark Christopher Wood
  • Patent number: 11016898
    Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: May 25, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Andrew Edmund Turner, George Patsilaras, Bohuslav Rychlik, Wesley James Holland, Jeffrey Shabel, Simon Peter William Booth
  • Patent number: 11016126
    Abstract: Current measurement apparatus comprises a measurement arrangement and a signal source. The measurement arrangement is configured to measure a current signal drawn by a load. The signal source is operative to apply a reference input signal to the measurement arrangement whereby an output signal from the measurement arrangement comprises a load output signal corresponding to the load drawn current signal and a reference output signal corresponding to the reference input signal.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: May 25, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Jonathan Ephraim David Hurwitz, Seyed Amir Ali Danesh, William Michael James Holland
  • Publication number: 20210150770
    Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides hardware logic to apply a numerical transform to matrix data to increase the sparsity of the data. Increasing the sparsity may result in a higher compression ratio when the matrix data is compressed.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 20, 2021
    Applicant: Intel Corporation
    Inventors: ABHISHEK R. APPU, PRASOONKUMAR SURTI, JILL BOYCE, SUBRAMANIAM MAIYURAN, MICHAEL APODACA, ADAM T. LAKE, JAMES HOLLAND, VASANTH RANGANATHAN, ALTUG KOKER, LIDONG XU, NIKOS KABURLASOS
  • Publication number: 20210150663
    Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 20, 2021
    Applicant: Intel Corporation
    Inventors: Subramaniam Maiyuran, Durgaprasad Bilagi, Joydeep Ray, Scott Janus, Sanjeev Jahagirdar, Brent Insko, Lidong Xu, Abhishek R. Appu, James Holland, Vasanth Ranganathan, Nikos Kaburlasos, Altug Koker, Xinmin Tian, Guei-Yuan Lueh, Changliang Wang
  • Publication number: 20210151287
    Abstract: A method and system for analyzing a specimen in a microscope are disclosed.
    Type: Application
    Filed: July 19, 2018
    Publication date: May 20, 2021
    Inventors: Anthony Hyde, James Holland, Simon Burgess, Peter Statham, Philippe Pinard, James Corrin
  • Publication number: 20210149763
    Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 20, 2021
    Applicant: Intel Corporation
    Inventors: Vasanth Ranganathan, Joydeep Ray, Abhishek R. Appu, Nikos Kaburlasos, Lidong Xu, Subramaniam Maiyuran, Altug Koker, Naveen Matam, James Holland, Brent Insko, Sanjeev Jahagirdar, Scott Janus, Durgaprasad Bilagi, Xinmin Tian
  • Patent number: 11006127
    Abstract: An exemplary method for intelligent compression uses a foveated-compression approach. First, the location of a fixation point within an image frame is determined. Next, the image frame is sectored into two or more sectors such that one of the two or more sectors is designated as a fixation sector and the remaining sectors are designated as foveation sectors. A sector may be defined by one or more tiles within the image frame. The fixation sector includes the particular tile that contains the fixation point and is compressed according to a lossless compression algorithm. The foveation sectors are compressed according to lossy compression algorithms. As the locations of foveation sectors increase in angular distance from the location of the fixation sector, a compression factor may be increased.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: May 11, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Meghal Varia, Serag Gadelrab, Wesley James Holland, Joseph Cheung, Dam Backer, Tom Longo
  • Publication number: 20210125664
    Abstract: Systems, methods, and computer-readable media are provided for providing pose estimation in extended reality systems. An example method can include tracking, in a lower-power processing mode using a set of lower-power circuit elements on an integrated circuit, a position and orientation of a computing device during a lower-power processing period, the set of lower-power circuit elements including a static random-access memory (SRAM); suspending, based on a triggering event, the tracking in the lower-power processing mode; initiating a higher-power processing mode for tracking the position and orientation of the computing device during a higher-power processing period; and tracking, in the higher-power processing mode using a set of higher-power circuit elements on the integrated circuit and a dynamic random-access memory (DRAM), the position and orientation of the computing device during the higher-power processing period.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 29, 2021
    Inventors: Wesley James HOLLAND, Mehrad TAVAKOLI, Injoon HONG, Huang HUANG, Simon Peter William BOOTH, Gerhard REITMAYR
  • Publication number: 20210105466
    Abstract: Techniques related to distributing the video encoding processing of an input video across hardware and software systems. Such techniques include evaluating the content of the video and determine whether or the encoding operation is best to be done on the hardware system only, software system only or a hybrid hardware and software system.
    Type: Application
    Filed: December 18, 2020
    Publication date: April 8, 2021
    Applicant: Intel Corporation
    Inventors: Brinda Ganesh, Nilesh Jain, Sumit Mohan, Faouzi Kossentini, Jill Boyce, James Holland, Zhijun Lei, Chekib Nouira, Foued Ben Amara, Hassene Tmar, Sebastian Possos, Craig Hurst