Abstract: A recursive Analog Content Addressable Memory (ACAM) device includes a first comparison stage and a second comparison stage. The first comparison stage includes a first match line, a first base segment comparator connected between the first match line and a reference node, a first incremented segment comparator, and a first pass transistor. The first pass transistor and the first incremented segment comparator are connected in series between the first match line and the reference node. The second comparison stage includes a first inverter connected to the first pass transistor, a second match line connected to the first inverter, and a second base segment comparator connected between the second match line and the reference node. The device enables efficient comparison of multi-bit values.

Abstract: A dynamic analog content addressable memory (CAM) cell uses volatile memory to store a range. The dynamic analog CAM cell includes an upper bound circuit and a lower bound circuit. The upper bound circuit includes a first pull-down transistor and a first controlled current generator. The first controlled current generator is configured to store an upper bound of the range in a first dynamic memory circuit, and to activate the first pull-down transistor when an analog input value is greater than the upper bound of the range. The lower bound circuit includes a second pull-down transistor and a second controlled current generator. The second controlled current generator is configured to store a lower bound of the range in a second dynamic memory circuit, and to activate the second pull-down transistor when the analog input value is less than the lower bound of the range.

Abstract: A recursive Analog Content Addressable Memory (ACAM) device includes a first comparison stage and a second comparison stage. The first comparison stage includes a first match line, a first base segment comparator connected between the first match line and a reference node, a first incremented segment comparator, and a first pass transistor. The first pass transistor and the first incremented segment comparator are connected in series between the first match line and the reference node. The second comparison stage includes a first inverter connected to the first pass transistor, a second match line connected to the first inverter, and a second base segment comparator connected between the second match line and the reference node. The device enables efficient comparison of multi-bit values.

Abstract: In certain examples, an analog content addressable memory (ACAM) component includes a plurality of transistors and a memristor. A gate terminal of a first transistor of the plurality of transistors is coupled to a data line for applying an input current, another terminal of the first transistor is coupled to the memristor and a gate terminal of a second transistor, another terminal of the second transistor is coupled to a match line, and the ACAM component is configured to provide a match result based on the input current and a value programmed to the memristor.

Abstract: Examples of the present technology provide heterogeneous (i.e., multi-chip) ASIC-memristor integrations that enable high voltage-dependent precision memristor programming while preserving optimal ASIC performance/capabilities. Examples achieve these advantages by “de-coupling” memristor hardware from ASIC chip. Accordingly, a heterogeneous ASIC-memristor integration of the present technology may comprise an ASIC chip packaged onto a functional “memristor-interposer” chip. The memristor interposer may serve both a functional and structural purpose. Namely, memristors of the memristor interposer can be leveraged in conjunction with the ASIC for processing/computation functions—while connections within the memristor interposer route signals between ASIC and computing system (e.g., between the ASIC and a printed circuit board).

Abstract: A device that includes a first circuit, an analog content addressable memory (ACAM), and a result analyzer is disclosed. The first circuit can be programmed with a matrix. The first circuit can be configured to receive an input vector comprising a first set of values; perform a matrix multiplication by multiplying the input vector by the matrix to obtain a matrix multiplication result; and output the matrix multiplication result, where the matrix multiplication result corresponds to a feature vector. The ACAM can be configured to receive the feature vector and perform an operation using the feature vector to obtain a set of output match results. The result analyzer can be configured to output a machine learning algorithm result based on the set of output match results. In some implementations, the matrix multiplication can be performed using a dot product engine of the first circuit.

Abstract: A dynamic analog content addressable memory (CAM) cell uses volatile memory to store a range. The dynamic analog CAM cell includes an upper bound circuit and a lower bound circuit. The upper bound circuit includes a first pull-down transistor and a first controlled current generator. The first controlled current generator is configured to store an upper bound of the range in a first dynamic memory circuit, and to activate the first pull-down transistor when an analog input value is greater than the upper bound of the range. The lower bound circuit includes a second pull-down transistor and a second controlled current generator. The second controlled current generator is configured to store a lower bound of the range in a second dynamic memory circuit, and to activate the second pull-down transistor when the analog input value is less than the lower bound of the range.

Abstract: Examples of the present technology provide heterogeneous (i.e., multi-chip) ASIC-memristor integrations that enable high voltage-dependent precision memristor programming while preserving optimal ASIC performance/capabilities. Examples achieve these advantages by “de-coupling” memristor hardware from ASIC chip. Accordingly, a heterogeneous ASIC-memristor integration of the present technology may comprise an ASIC chip packaged onto a functional “memristor-interposer” chip. The memristor interposer may serve both a functional and structural purpose. Namely, memristors of the memristor interposer can be leveraged in conjunction with the ASIC for processing/computation functions—while connections within the memristor interposer route signals between ASIC and computing system (e.g., between the ASIC and a printed circuit board).

Abstract: In example implementations, an integrated characterization vehicle is provided. The integrated characterization vehicle includes a memristor, a configuration cache and an analog measurement tile. The memristor has a driving unit to limit an amount of current that is driven through the memristor during testing. The configuration cache provides test parameters to control the testing of the memristor. The analog measurement tile provides a voltage to the memristor in accordance with the test parameters and to record a response of the memristor.

Abstract: In example implementations, an integrated characterization vehicle is provided. The integrated characterization vehicle includes a memristor, a configuration cache and an analog measurement tile. The memristor has a driving unit to limit an amount of current that is driven through the memristor during testing. The configuration cache provides test parameters to control the testing of the memristor. The analog measurement tile provides a voltage to the memristor in accordance with the test parameters and to record a response of the memristor.

Abstract: A thermal sensing system may comprise a plurality of remote sensors distributed across an integrated circuit (IC). Each of the plurality of remote sensors provides an analog signal that varies as a function of temperature of a respective region of the IC where each respective remote sensor is located. A central system, forming part of the IC, samples the analog signals from the plurality of remote sensors and converts the sampled analog signals to corresponding digital values.

Abstract: A method for calibrating a voltage controlled oscillator (VCO) comprising applying a plurality of known voltages to the input of a VCO, monitoring, for each of the voltages, an output count from the VCO over a set interval, and storing the output counts for each voltage. Also disclosed is a system for calibrating a voltage controlled oscillator (VCO) comprising a plurality of known voltages, wherein the known voltage are connectable to the VCO, and a controller coupled to the output of the VCO, wherein the controller maintains a calibration table of VCO output counts for selected voltage inputs.