Patents by Inventor James Imber

James Imber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260065081
    Abstract: A method and data processing system using a processor implement a neural network containing at least one matrix multiplication operation. A set of operations to which the matrix multiplication operations are mapped is evaluated, the set of operations including at least one convolution operation, to thereby evaluate the matrix multiplication operation, whereby the processor is adapted to multiply the same set of weights simultaneously by multiple sets of input data elements in parallel at multiple processing elements.
    Type: Application
    Filed: November 6, 2025
    Publication date: March 5, 2026
    Inventors: Biswarup Choudhury, Aria Ahmadi, James Imber, Cagatay Dikici, Timothy Atherton
  • Publication number: 20260044707
    Abstract: Hierarchical methods for selecting fixed point number formats with reduced mantissa bit lengths for representing values input to, and/or output, from, the layers of a DNN. The methods begin with one or more initial fixed point number formats for each layer. The layers are divided into subsets of layers and the mantissa bit lengths of the fixed point number formats are iteratively reduced from the initial fixed point number formats on a per subset basis. If a reduction causes the output error of the DNN to exceed an error threshold, then the reduction is discarded, and no more reductions are made to the layers of the subset. Otherwise a further reduction is made to the fixed point number formats for the layers in that subset. Once no further reductions can be made to any of the subsets the method is repeated for continually increasing numbers of subsets until a predetermined number of layers per subset is achieved.
    Type: Application
    Filed: October 17, 2025
    Publication date: February 12, 2026
    Inventors: James Imber, Linling Zhang, Cagatay Dikici
  • Publication number: 20260044733
    Abstract: Methods for selecting fixed point number formats for representing values input to and/or output from layers of a Deep Neural Network (DNN) which take into account the impact of the fixed point number formats for a particular layer in the DNN. The fixed point number format(s) used to represent sets of values input to and/or output from a layer are selected one layer at a time in a predetermined sequence wherein any layer is preceded in the sequence by the layer(s) from which it depends. The fixed point number format(s) for each layer is/are selected based on the error in the output of the DNN associated with the fixed point number formats. Once the fixed point number format(s) for a layer has/have been selected any calculation of the error in the output of the DNN for a subsequent layer in the sequence is based on that layer being configured to use the selected fixed point number formats.
    Type: Application
    Filed: October 15, 2025
    Publication date: February 12, 2026
    Inventor: James Imber
  • Publication number: 20260044708
    Abstract: Hierarchical methods for selecting fixed point number formats with reduced mantissa bit lengths for representing values input to, and/or output, from, the layers of a DNN. The methods begin with one or more initial fixed point number formats for each layer. The layers are divided into subsets of layers and the mantissa bit lengths of the fixed point number formats are iteratively reduced from the initial fixed point number formats on a per subset basis. If a reduction causes the output error of the DNN to exceed an error threshold, then the reduction is discarded, and no more reductions are made to the layers of the subset. Otherwise a further reduction is made to the fixed point number formats for the layers in that subset. Once no further reductions can be made to any of the subsets the method is repeated for continually increasing numbers of subsets until a predetermined number of layers per subset is achieved.
    Type: Application
    Filed: October 17, 2025
    Publication date: February 12, 2026
    Inventors: James Imber, Linling Zhang, Cagatay Dikici
  • Patent number: 12524649
    Abstract: A computer-implemented method of selecting a number format for representing two or more values of a recurrent neural network (RNN) for use in configuring a hardware implementation of the RNN, includes receiving a representation of the RNN; implementing the representation of the RNN as a test neural network for operation on a sequence of test inputs, each step of the test neural network comprising an instance of the two or more values of the RNN; operating the test neural network for a plurality of steps on the sequence of test inputs and collecting statistics for provision to a number format selection algorithm; and applying a number format selection algorithm to the statistics so as to derive a common number format for the plurality of instances of the two or more values of the RNN.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: January 13, 2026
    Assignee: Imagination Technologies Limited
    Inventors: Muhammad Asad, Elia Condorelli, James Imber, Cagatay Dikici
  • Patent number: 12488253
    Abstract: A method and data processing system implement a neural network containing at least one matrix multiplication operation. The matrix multiplication operation is mapped to a graph of neural network operations including at least one transformation and at least one convolution. The at least one convolution is implemented in fixed-function hardware of a neural network accelerator.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: December 2, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Biswarup Choudhury, Aria Ahmadi, James Imber, Cagatay Dikici, Timothy Atherton
  • Publication number: 20250148264
    Abstract: A windowed operation is implemented in at least three traversed dimensions. The windowed operation applies a window having at least three dimensions to data having at least three traversed dimensions, with shifts of the window in all three traversed dimensions. Two dimensions of the at least three traversed dimensions are selected, and the windowed operation is mapped to a plurality of constituent 2-D windowed operations in the selected two dimensions, the 2-D windowed operations applying a slice of the window to a slice of the data, with shifts of the slice of the window in only two dimensions. Each of the plurality of 2-D windowed operations is implemented by at least one hardware accelerator, each 2-D windowed operation producing a respective partial result, and the partial results are assembled to produce the result of the windowed operation.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Inventors: Ivaxi Sheth, Aria Ahmadi, James Imber, Cagatay Dikici
  • Publication number: 20250131257
    Abstract: A method of configuring a hardware implementation of a Convolutional Neural Network (CNN), the method comprising: determining, for each of a plurality of layers of the CNN, a first number format for representing weight values in the layer based upon a distribution of weight values for the layer, the first number format comprising a first integer of a first predetermined bit-length and a first exponent value that is fixed for the layer; determining, for each of a plurality of layers of the CNN, a second number format for representing data values in the layer based upon a distribution of expected data values for the layer, the second number format comprising a second integer of a second predetermined bit-length and a second exponent value that is fixed for the layer; and storing the determined number formats for use in configuring the hardware implementation of a CNN.
    Type: Application
    Filed: December 24, 2024
    Publication date: April 24, 2025
    Inventors: Clifford Gibson, James Imber
  • Publication number: 20250068693
    Abstract: Methods and systems for performing a convolution transpose operation between an input tensor having a plurality of input elements and a filter comprising a plurality of filter weights. The method includes: dividing the filter into a plurality of sub-filters; performing, using hardware logic, a convolution operation between the input tensor and each of the plurality of sub-filters to generate a plurality of sub-output tensors, each sub-output tensor comprising a plurality of output elements; and interleaving, using hardware logic, the output elements of the plurality of sub-output tensors to form a final output tensor for the convolution transpose.
    Type: Application
    Filed: November 15, 2024
    Publication date: February 27, 2025
    Inventors: Cagatay Dikici, Clifford Gibson, James Imber
  • Publication number: 20250068883
    Abstract: Hierarchical methods for selecting fixed point number formats with reduced mantissa bit lengths for representing values input to, and/or output, from, the layers of a DNN. The methods begin with one or more initial fixed point number formats for each layer. The layers are divided into subsets of layers and the mantissa bit lengths of the fixed point number formats are iteratively reduced from the initial fixed point number formats on a per subset basis. If a reduction causes the output error of the DNN to exceed an error threshold, then the reduction is discarded, and no more reductions are made to the layers of the subset. Otherwise a further reduction is made to the fixed point number formats for the layers in that subset. Once no further reductions can be made to any of the subsets the method is repeated for continually increasing numbers of subsets until a predetermined number of layers per subset is achieved.
    Type: Application
    Filed: November 14, 2024
    Publication date: February 27, 2025
    Inventors: James Imber, Linling Zhang, Cagatay Dikici
  • Patent number: 12217161
    Abstract: A method of configuring a hardware implementation of a Convolutional Neural Network (CNN), the method comprising: determining, for each of a plurality of layers of the CNN, a first number format for representing weight values in the layer based upon a distribution of weight values for the layer, the first number format comprising a first integer of a first predetermined bit-length and a first exponent value that is fixed for the layer; determining, for each of a plurality of layers of the CNN, a second number format for representing data values in the layer based upon a distribution of expected data values for the layer, the second number format comprising a second integer of a second predetermined bit-length and a second exponent value that is fixed for the layer; and storing the determined number formats for use in configuring the hardware implementation of a CNN.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: February 4, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Clifford Gibson, James Imber
  • Patent number: 12198307
    Abstract: A method of rendering an image of a 3-D scene includes rendering a noisy image at a first resolution; obtaining one or more guide channels at the first resolution, and obtaining one or more corresponding guide channels at a second resolution. The second resolution may be the same resolution as, or a higher resolution than, the first resolution. For each of a plurality of local neighbourhoods, the method comprises: calculating the parameters of a model that approximates the noisy image as a function of the one or more guide channels (at the first resolution), and applying the calculated parameters to the one or more guide channels at the second resolution, to produce a denoised image at the second resolution.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: January 14, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Szabolcs Cséfalvay, James Imber, David Walton, Insu Yu
  • Patent number: 12198034
    Abstract: A data processing system and method are disclosed, for implementing a windowed operation in at least three traversed dimensions. The data processing system maps the windowed operation in at least three traversed dimensions to a plurality of constituent windowed operations in two traversed dimensions. This plurality of 2-D windowed operations is implemented as such in at least one hardware accelerator. The data processing system assembles the results of the constituent 2-D windowed operations to produce the result of the windowed operation in at least three traversed dimensions.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: January 14, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Ivaxi Sheth, Aria Ahmadi, James Imber, Cagatay Dikici
  • Publication number: 20250005719
    Abstract: A differentiable module of a differentiable model of an image signal processor having a pipeline of functional blocks, wherein the differentiable module is configured to implement a single functional block of the pipeline, the differentiable module including base logic configured to receive an input image signal and to process the received input image signal by performing a base image processing function that represents a task of the functional block of the pipeline implemented by the module; a refinement function configured to receive the input image signal and to process the received input image signal in parallel to the processing of the received input image signal by the base logic; and combining logic configured to combine the processed image signal from the base logic and the processed image signal from the refinement function to determine an output image signal to be outputted from the differentiable module. A corresponding method is also described.
    Type: Application
    Filed: June 27, 2024
    Publication date: January 2, 2025
    Inventor: James Imber
  • Publication number: 20250005718
    Abstract: Training apparatus for training a differentiable model of an image signal processor having a pipeline of separate image signal processing functions, includes processors configured to receive a reference image; and train a first differentiable module to perform a first image signal processing function, whilst not training other differentiable modules, by iteratively inputting, to the differentiable model a degraded image signal that represents a known degradation of the reference image, the degradation being related to the first image signal processing function; processing the degraded image signal using the differentiable model to produce a first processed image including using the first differentiable module to perform the first image signal processing function; calculating an error between the first processed image and the reference image; and updating the first image processing function performed by the first differentiable module based on the calculated error without updating the image processing function
    Type: Application
    Filed: June 27, 2024
    Publication date: January 2, 2025
    Inventor: James Imber
  • Patent number: 12174910
    Abstract: Methods and systems for performing a convolution transpose operation between an input tensor having a plurality of input elements and a filter comprising a plurality of filter weights. The method includes: dividing the filter into a plurality of sub-filters; performing, using hardware logic, a convolution operation between the input tensor and each of the plurality of sub-filters to generate a plurality of sub-output tensors, each sub-output tensor comprising a plurality of output elements; and interleaving, using hardware logic, the output elements of the plurality of sub-output tensors to form a final output tensor for the convolution transpose.
    Type: Grant
    Filed: January 29, 2024
    Date of Patent: December 24, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Cagatay Dikici, Clifford Gibson, James Imber
  • Patent number: 12175349
    Abstract: Hierarchical methods for selecting fixed point number formats with reduced mantissa bit lengths for representing values input to, and/or output, from, the layers of a DNN. The methods begin with one or more initial fixed point number formats for each layer. The layers are divided into subsets of layers and the mantissa bit lengths of the fixed point number formats are iteratively reduced from the initial fixed point number formats on a per subset basis. If a reduction causes the output error of the DNN to exceed an error threshold, then the reduction is discarded, and no more reductions are made to the layers of the subset. Otherwise a further reduction is made to the fixed point number formats for the layers in that subset. Once no further reductions can be made to any of the subsets the method is repeated for continually increasing numbers of subsets until a predetermined number of layers per subset is achieved.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: December 24, 2024
    Assignee: Imagination Technologies Limited
    Inventors: James Imber, Linling Zhang, Cagatay Dikici
  • Publication number: 20240412056
    Abstract: Hardware implementations of Deep Neural Networks (DNNs) and related methods with a variable output data format. Specifically, in the hardware implementations and methods described herein the hardware implementation is configured to perform one or more hardware passes to implement a DNN wherein during each hardware pass the hardware implementation receives input data for a particular layer, processes that input data in accordance with the particular layer (and optionally one or more subsequent layers), and outputs the processed data in a desired format based on the layer, or layers, that are processed in the particular hardware pass. In particular, when a hardware implementation receives input data to be processed, the hardware implementation also receives information indicating the desired format for the output data of the hardware pass and the hardware implementation is configured to, prior to outputting the processed data convert the output data to the desired format.
    Type: Application
    Filed: August 23, 2024
    Publication date: December 12, 2024
    Inventors: Chris Martin, David Hough, Paul Brasnett, Cagatay Dikici, James Imber, Clifford Gibson
  • Patent number: 12165045
    Abstract: Hardware implementations of DNNs and related methods with a variable output data format. Specifically, in the hardware implementations and methods described herein the hardware implementation is configured to perform one or more hardware passes to implement a DNN wherein during each hardware pass the hardware implementation receives input data for a particular layer, processes that input data in accordance with the particular layer (and optionally one or more subsequent layers), and outputs the processed data in a desired format based on the layer, or layers, that are processed in the particular hardware pass. In particular, when a hardware implementation receives input data to be processed, the hardware implementation also receives information indicating the desired format for the output data of the hardware pass and the hardware implementation is configured to, prior to outputting the processed data convert the output data to the desired format.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: December 10, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Chris Martin, David Hough, Paul Brasnett, Cagatay Dikici, James Imber, Clifford Gibson
  • Publication number: 20240394525
    Abstract: A histogram-based method of selecting a fixed point number format for representing a set of values input to, or output from, a layer of a Deep Neural Network (DNN). The method comprises obtaining a histogram that represents an expected distribution of the set of values of the layer, each bin of the histogram is associated with a frequency value and a representative value in a floating point number format; quantising the representative values according to each of a plurality of potential fixed point number formats; estimating, for each of the plurality of potential fixed point number formats, the total quantisation error based on the frequency values of the histogram and a distance value for each bin that is based on the quantisation of the representative value for that bin; and selecting the fixed point number format associated with the smallest estimated total quantisation error as the optimum fixed point number format for representing the set of values of the layer.
    Type: Application
    Filed: August 5, 2024
    Publication date: November 28, 2024
    Inventors: James Imber, Cagatay Dikici