Abstract: A method of placing a clock signal supply network in a design representation for an integrated circuit. The design representation may comprise a plurality of clockable circuit cells. The method may comprise identifying a first of the clockable circuit cells in the design representation. The method may further comprise identifying a second of the clockable circuit cells in the design representation. The second clockable circuit cell may have a clock timing dependent relation relative to the first clockable circuit cell. The method may further comprise configuring the clock signal supply network. The clock signal supply network may be configured to supply respective clock signals to the first and said second clockable circuit cells. The clock signal supply network may be configured to route the respective clock signals such that a timing difference between the respective clock signals is protected from process, voltage and temperature (PVT) influences.

Abstract: A method and system for improving ASIC routability is disclosed. In a first aspect of the present invention, the method and system include performing an initial cell placement process on an ASIC design; performing a global routing process and creating global routing data, including congestion data; and repeating the initial cell placement process using the congestion data as input, such that cell and routing density in the ASIC design is reduced, thereby reducing routing congestion. In a second aspect of the present invention, the method and system further include performing a placement refinement and buffer insertion process; performing a repeater removal process that uses the congestion data as input and removes buffers from the congested areas; and repeating the placement refinement process, such that global nets are routed around the congested areas.