Abstract: In some embodiments, a computer system applies a time of day setting to a virtual environment. In some embodiments, the time of day setting is updated based on an event. In some embodiments, a computer system displays content in an expanded display mode. In some embodiments, computer systems join a communication session while maintaining display of respective environments. In some embodiments, a computer system moves a portal based on user movement. In some embodiments, computer systems share a virtual environment. Computer systems can display media with simulated lighting. Computer systems can share an environment. In some embodiments, a computer system selects a position relative to content. A computer system can present representations of communication session participants based on content. A computer system can present user interfaces to control visual appearances of an environment including media. Computer systems can change an appearance of an environment based on environmental modes.

Abstract: A drill bit includes a shank defining a longitudinal axis and a cutting edge extending radially outward relative to the longitudinal axis. The cutting edge is configured to remove material from a workpiece along a cutting path during a cutting operation. The drill bit further includes a plurality of scoring elements positioned within the cutting path and configured to contact the workpiece before the cutting edge during the cutting operation.

Abstract: The CRC for the CPS Header of an ATM AAL2 cell is generated by a CRC generator which uses the 8 bits of the CID field to generate partial 5 bits CRCs which are loaded in a first table. The 6 bits LI field and 5 bits UUI field are added to the partial 5 bits CRC to form 16 bits. The CRC generator uses the 2.sup.16 bits to generate a second CRC table. The CRC for a particular CPS header is generated by correlating bits in the CID field, LI field and UUI field with the two tables.

Abstract: The CRC for the CPS Header of an ATM AAL2 cell is generated by a CRC generator which uses the 8 bits of the CID field to generate partial 5 bits CRCs which are loaded in a first table. The 6 bits LI field and 5 bits UUI field are added to the partial 5 bits CRC to form 16 bits. The CRC generator uses the 2.sup.16 bits to generate a second CRC table. The CRC for a particular CPS header is generated by correlating bits in the CID field, LI field and UUI field with the two tables.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processor memory system, which may include a processor and a memory controller in communication with the processor through a bus. The memory controller may include a delay circuit to receive an early read indicator corresponding to read data from a memory, the delay circuit to delay the early read indicator in accordance with a pre-determined delay such that the early read indicator is passed to the bus in advance of the read data, and a delay adjustment circuit to dynamically adjust the pre-determined delay associated with the delay circuit responsive to a change in operational speed of the processor or the bus.

Abstract: The present invention provides a system and method for a computer controlled test system in which the computer can change and monitor the compound observable state of an electronic device or telephone during testing procedure. In the preferred embodiment of the invention, the compound observable state of the electronic device includes a display bit map file or the status of lights or buttons. The compound observable state can be evaluated by the computer in real-time to alert nearby operators of a failure (i.e. a telephone that needs to be rebooted) or malfunction (not rising to the level of a failure). Also, the data related to the compound observable state can be stored in the computer for later review to assist in debugging the telephone's software.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a storage device, circuitry for providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to the storage device that can be speculatively issued, and circuitry for intermixing demand accesses and speculative accesses in accordance with the speculative access threshold.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system is provided. A scheduling algorithm pre-computes return time data for data connected to DRAM buffer chips and stores the return time data in a table. The return time data is expressed as data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.

Abstract: A method for generating reliability tests for a telephone system is based upon sampling an orthogonal array which covers various combinations of test parameters. Field data is collected of actual telephone activity on a telephone system. The field data is evaluated so as to determine call-mix characteristics. Probabilistic weights for the different call-mix characteristics are obtained, and then the probabilistic weights are used to sample the test case scenarios generated in the orthogonal array which have the same call-mix characteristics. These test case scenarios are used to run tests on the telephone system. These tests are preferably performed using automated test scripts. After the test data is collected, reliability metrics are calculated from the test data.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold.

Abstract: A method and system for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system. A scheduling algorithm pre-computes return time data for data connected to all DRAM buffer chips and stores the return time data in a table. The return time data is expressed as a set of data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector representing a compilation of data return time vectors of all executing requests to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.

Abstract: Methods and system for reducing latency associated with a read operation in a processor memory system are provided. In one implementation, the method includes receiving an early indicator corresponding to read data from a memory, delaying the early indicator in accordance with a pre-determined delay such that the early read indicator is passed to a bus in advance of the read data; and dynamically adjusting the pre-determined delay using an adjustment delay circuit, the pre-determined delay being adjusted responsive to a change in operational speed of the bus or change in operational speed of a processor coupled to the bus.

Abstract: In one embodiment, a method is disclosed for timing responses to a plurality of memory requests. The method can include sending a plurality of memory requests to a plurality of in-line memory modules. The requests can be sent over a channel from a plurality of channels, where each channel can have a plurality of lanes. The method can receive responses to the plurality of memory requests over the channel and monitor the response to detect a timing relationship between at least two lanes from the plurality of lanes. In addition, the method can adjust a timing of a register loading and unloading sequence in response to the monitoring of multiple lanes and channels. Other embodiments are also disclosed.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a storage device, circuitry for providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to the storage device that can be speculatively issued, and circuitry for intermixing demand accesses and speculative accesses in accordance with the speculative access threshold.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold.

Abstract: A tiltable micromirror device is disclosed in which a micromirror is suspended by a progressive linkage with an electrostatic actuator (e.g. a vertical comb actuator or a capacitive plate electrostatic actuator) being located beneath the micromirror. The progressive linkage includes a pair of torsion springs which are connected together to operate similar to a four-bar linkage with spring joints. The progressive linkage provides a non-linear spring constant which can allow the micromirror to be tilted at any angle within its range substantially free from any electrostatic instability or hysteretic behavior.

Abstract: The present invention provides a system and method for a computer controlled test system in which the computer can change and monitor the compound observable state of an electronic device or telephone during testing procedure. In the preferred embodiment of the invention, the compound observable state of the electronic device includes a display bit map file or the status of lights or buttons. The compound observable state can be evaluated by the computer in real-time to alert nearby operators of a failure (i.e. a telephone that needs to be rebooted) or malfunction (not rising to the level of a failure). Also, the data related to the compound observable state can be stored in the computer for later review to assist in debugging the telephone's software.

Abstract: A method for generating reliability tests for a telephone system is based upon sampling an orthogonal array which covers various combinations of test parameters. Field data is collected of actual telephone activity on a telephone system. The field data is evaluated so as to determine call-mix characteristics. Probabilistic weights for the different call-mix characteristics are obtained, and then the probabilistic weights are used to sample the test case scenarios generated in the orthogonal array which have the same call-mix characteristics. These test case scenarios are used to run tests on the telephone system. These tests are preferably performed using automated test scripts. After the test data is collected, reliability metrics are calculated from the test data.

Abstract: An active hinge apparatus is disclosed which can be used to raise a micromechanical structure (e.g. a plate or micromirror) on a substrate. The active hinge apparatus utilizes one or more of teeth protruding outward from an axle which also supports the micromechanical structure on one end thereof. A rack is used to engage the teeth and rotate the axle to raise the micromechanical structure and tilt the structure at an angle to the substrate. Motion of the rack is provided by an actuator which can be a mechanically-powered actuator, or alternately an electrostatic comb actuator or a thermal actuator. A latch can be optionally provided in the active hinge apparatus to lock the micromechanical structure in an “erected” position.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system is provided. A scheduling algorithm pre-computes return time data for data connected to DRAM buffer chips and stores the return time data in a table. The return time data is expressed as data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.