Patents by Inventor James J. Bennett

James J. Bennett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7519553
    Abstract: The present invention employs data processing systems to handle debt collection by formulation the collections process as a Markov Decision Process with constrained resources, thus making it possible automatically to generate an optimal collections policy with respect to maximizing long-term expected return throughout the course of a collections process, subject to constraints on the available resources possibly in multiple organizations. This is accomplished by coupling data modeling and resource optimization within the constrained Markov Decision Process formulation and generating optimized rules based on constrained reinforcement learning process comprising applied on the basis of past historical data.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: April 14, 2009
    Assignee: International Business Machines Corporation
    Inventors: Naoki Abe, James J. Bennett, David L. Jensen, Richard D. Lawrence, Prem Melville, Edwin Peter Dawson Pednault, Cezar Pendus, Chandan Karrem Reddy, Vincent Philip Thomas
  • Publication number: 20080275800
    Abstract: The present invention employs data processing systems to handle debt collection by formulation the collections process as a Markov Decision Process with constrained resources, thus making it possible automatically to generate an optimal collections policy with respect to maximizing long-term expected return throughout the course of a collections process, subject to constraints on the available resources possibly in multiple organizations. This is accomplished by coupling data modeling and resource optimization within the constrained Markov Decision Process formulation and generating optimized rules based on constrained reinforcement learning process comprising applied on the basis of past historical data.
    Type: Application
    Filed: May 2, 2007
    Publication date: November 6, 2008
    Inventors: Naoki Abe, James J. Bennett, David L. Jensen, Richard D. Lawrence, Prem Melville, Edwin Peter Dawson Pednault, Cezar Pendus, Chandan Karrem Reddy, Vincent Philip Thomas
  • Patent number: 7100058
    Abstract: A programmable power management integrated circuit includes analog input monitors that receive analog input signals that correspond to voltage, current, or temperature measurements. The analog input monitors apply programmable thresholds to the measurements and output the results to a programmable logic device, which may generate various status and/or control signals to the system being monitored. The programmable logic device controls FET drivers that can switch on and off power to the monitored system. The programmable power management integrated circuit may also comprise an internal oscillator, a serial interface, an in-system programmable interface, a joint test action group interface, a memory that stores identification information, and a register for capturing system information during power-down.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: August 29, 2006
    Assignee: Lattice Semiconductor Corporation
    Inventors: Jock F. Tomlinson, David C. Wilkinson, James J. Bennett, Douglas C. Morse
  • Patent number: 6735706
    Abstract: A programmable power management integrated circuit includes analog input monitors that receive analog input signals that correspond to voltage, current, or temperature measurements. The analog input monitors apply programmable thresholds to the measurements and output the results to a programmable logic device, which may generate various status and/or control signals to the system being monitored. The programmable logic device controls FET drivers that can switch on and off power to the monitored system. The programmable power management integrated circuit may also comprise an internal oscillator, a serial interface, an in-system programmable interface, a joint test action group interface, a memory that stores identification information, and a register for capturing system information during power-down.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: May 11, 2004
    Assignee: Lattice Semiconductor Corporation
    Inventors: Jock F. Tomlinson, David C. Wilkinson, James J. Bennett, Douglas C. Morse
  • Publication number: 20020104031
    Abstract: A programmable power management integrated circuit includes analog input monitors that receive analog input signals that correspond to voltage, current, or temperature measurements. The analog input monitors apply programmable thresholds to the measurements and output the results to a programmable logic device, which may generate various status and/or control signals to the system being monitored. The programmable logic device controls FET drivers that can switch on and off power to the monitored system. The programmable power management integrated circuit may also comprise an internal oscillator, a serial interface, an in-system programmable interface, a joint test action group interface, a memory that stores identification information, and a register for capturing system information during power-down.
    Type: Application
    Filed: December 6, 2000
    Publication date: August 1, 2002
    Inventors: Jock F. Tomlinson, David C. Wilkinson, James J. Bennett, Douglas C. Morse