Abstract: A computer-implemented method for marking load and store instruction overlap in a processor pipeline is described. The method includes detecting a load instruction following a store instruction in an instruction stream. The load instruction and the store instruction include instruction text. The instruction text includes operand address information. The method includes comparing operand address information of the store instruction with operand address information of the load instruction to determine whether there is a memory image overlap in an issue queue between the operand address information of the store instruction and the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to determining that there is a memory image overlap.

Abstract: Examples of techniques for distance-based branch prediction are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method includes: determining, by a processing system, a potential return instruction address (IA) by determining whether a relationship is satisfied between a first target IA and a first branch IA; storing a second branch IA as a return when a target IA of a second branch matches a potential return IA for the second branch; and applying the potential return IA for the second branch as a predicted target IA of a predicted branch IA stored as a return.

Abstract: Embodiments are directed to a method for optimizing performance of a microprocessor. The method includes monitoring the performance of the microprocessor in each of a plurality of performance modes. The method further includes choosing a performance mode based on the monitoring. Thereafter, using the performance mode for a predetermined amount of time. Each of the plurality of performance modes is a branch prediction mode.

Abstract: A method includes a processor providing at least one line entry address tag in each line of a branch predictor; indexing into the branch predictor with a current line address to predict a taken branch's target address and a next line address; re-indexing into the branch predictor with one of a predicted next line address or a sequential next line address when the at least one line entry address tag does not match the current line address; using branch prediction content compared against a search address to predict a direction and targets of branches and determining when a new line address is generated; and re-indexing into the branch predictor with a corrected next line address when it is determined that one of the predicted next line address or the sequential next line address differs from the new line address.

Abstract: Embodiments relate to branch prediction using a pattern history table (PHT) that is indexed using a global path vector (GPV). An aspect includes receiving a search address by a branch prediction logic that is in communication with the PHT and the GPV. Another aspect includes starting with the search address, simultaneously determining a plurality of branch predictions by the branch prediction logic based on the PHT, wherein the plurality of branch predictions comprises one of: (i) at least one not taken prediction and a single taken prediction, and (ii) a plurality of not taken predictions. Another aspect includes updating the GPV by shifting an instruction identifier of a branch instruction associated with a taken prediction into the GPV, wherein the GPV is not updated based on any not taken prediction.

Abstract: Embodiments relate to branch prediction using a pattern history table (PHT) that is indexed using a global path vector (GPV). An aspect includes receiving a search address by a branch prediction logic that is in communication with the PHT and the GPV. Another aspect includes starting with the search address, simultaneously determining a plurality of branch predictions by the branch prediction logic based on the PHT, wherein the plurality of branch predictions comprises one of: (i) at least one not taken prediction and a single taken prediction, and (ii) a plurality of not taken predictions. Another aspect includes updating the GPV by shifting an instruction identifier of a branch instruction associated with a taken prediction into the GPV, wherein the GPV is not updated based on any not taken prediction.

Abstract: Embodiments include method, systems and computer program products for variable branch target buffer line size for compression. In some embodiments, a branch target buffer (BTB) congruence class for a line of a first parent array of a BTB may be determined. A threshold indicative of a maximum number branches to be stored in the line may be set. A branch may be received to store in the line of the first parent array. A determination may be made that storing the branch in the line would exceed the threshold and the line can be responsively split into an even half line and an odd half line.

Abstract: A method, system, and computer program product of utilizing branch prediction logic in a system that processes instructions that include a branch are described. The method includes identifying the branch as conventionally predictable or not conventionally predictable, and based on the branch being identified as not conventionally predictable according to the identifying, either foregoing branch prediction and reallocating, using a processor, the branch prediction logic to another thread of the instructions or performing, using the processor, the branch prediction and speculative execution of one or more of the instructions following the branch to obtain prediction information. Based on the performing the branch prediction and the speculative execution, the method also includes verifying a match between a branch end according to the instructions and a branch end according to the branch prediction prior to providing the prediction information to a second processor processing the instructions.

Abstract: A computer-implemented method for predicting a taken branch that ends an instruction stream in a pipelined high frequency microprocessor includes receiving, by a processor, a first instruction within a first instruction stream, the first instruction including a first instruction address. The computer-implemented method further includes searching, by the processor, a stream-based index accelerator predictor one time for the stream; determining, by the processor, a prediction for a branch ending the branch stream; influencing, by the processor, a metadata prediction engine based on the prediction; and updating, by the processor, a stream-based index accelerator predictor with information indicative of the prediction.

Abstract: A computer-implemented method for predicting a taken branch that ends an instruction stream in a pipelined high frequency microprocessor includes receiving, by a processor, a first instruction within a first instruction stream, the first instruction comprising a first instruction address; searching, by the processor, an index accelerator predictor one time for the stream; determining, by the processor, a prediction for a taken branch ending the branch stream; influencing, by the processor, a metadata prediction engine based on the prediction; observing a plurality of taken branches from the exit accelerator predictor; maintaining frequency information based on the observed taken branches; determining, based on the frequency information, an updated prediction of the observed plurality of taken branches; and updating, by the processor, the index accelerator predictor with the the updated prediction.

Abstract: A computer-implemented method for predicting a taken branch that ends an instruction stream in a pipelined high frequency microprocessor includes receiving, by a processor, a first instruction within a first instruction stream, the first instruction comprising a first instruction address; searching, by the processor, an index accelerator predictor one time for the stream; determining, by the processor, a prediction for a taken branch ending the branch stream; influencing, by the processor, a metadata prediction engine based on the prediction; observing a plurality of taken branches from the exit accelerator predictor; maintaining frequency information based on the observed taken branches; determining, based on the frequency information, an updated prediction of the observed plurality of taken branches; and updating, by the processor, the index accelerator predictor with the updated prediction.

Abstract: A system, method and computer program product for maintaining an age and validity of entries in a structure associated with a processor is disclosed. An age tracking matrix is created for the structure. Each row of the age tracking matrix corresponds to an entry of the structure and each column of the age tracking matrix corresponds to an entry of the structure. When initiating an entry: a row corresponding to the entry is determined and a field in the determined row that is on a diagonal of the matrix is marked. For each other field in the determined row, the values that are in a diagonal field that is in a same column of the field are copied into the field. A relative age of the entries is determined by counting a number of marked fields in a column of the age tracking matrix.

Abstract: A computer-implemented method includes determining, by a stream-based index accelerator predictor of a processor, a predicted stream length between an instruction address and a taken branch ending an instruction stream. A first-level branch predictor of a hierarchical asynchronous lookahead branch predictor of the processor is searched for a branch prediction in one or more entries in a search range bounded by the instruction address and the predicted stream length. A search of a second-level branch predictor of the hierarchical asynchronous lookahead branch predictor is triggered based on failing to locate the branch prediction in the search range.

Abstract: Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.

Abstract: Embodiments include a technique for caching of perceptron branch patterns using ternary content addressable memory. The technique includes defining a table of perceptrons, each perceptron having a plurality of weights with each weight being associated with a bit location in a history vector, and defining a TCAM, the TCAM having a number of entries, wherein each entry includes a number of bit pairs, the number of bit pairs being equal to a number of weights for each associated perceptron. The technique also includes associating the TCAM with an array of x-bit saturating counters, and performing a branch prediction for a history vector of a given branch, the branch prediction indicating a perceptron prediction. The technique includes determining a most influential bit location in the history vector, the most influential bit location having a greatest weight of an associated perceptron.

Abstract: Embodiments relate to multithreaded branch prediction. An aspect includes a system for dynamically evaluating how to share entries of a multithreaded branch prediction structure. The system includes a first-level branch target buffer coupled to a processor circuit. The processor circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with the search request, and searching for an entry corresponding to the search request in the first-level branch prediction structure. The entry is not allowed based on a thread state of the entry indicating that the entry has caused a problem on a thread associated with the thread state.

Abstract: Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.

Abstract: Embodiments are directed to a method for optimizing performance of a microprocessor. The method includes monitoring the performance of the microprocessor in each of a plurality of performance modes. The method further includes choosing a performance mode based on the monitoring. Thereafter, using the performance mode for a predetermined amount of time. Each of the plurality of performance modes is a branch prediction mode.

Abstract: A computer-implemented method for marking load and store instruction overlap in a processor pipeline is described. The method includes detecting a load instruction following a store instruction in an instruction stream. The load instruction and the store instruction include instruction text. The instruction text includes operand address information. The method includes comparing operand address information of the store instruction with operand address information of the load instruction to determine whether there is a memory image overlap in an issue queue between the operand address information of the store instruction and the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to determining that there is a memory image overlap.

Abstract: Embodiments include a technique for caching of perceptron branch patterns using ternary content addressable memory. The technique includes defining a table of perceptrons, each perceptron having a plurality of weights with each weight being associated with a bit location in a history vector, and defining a TCAM, the TCAM having a number of entries, wherein each entry includes a number of bit pairs, the number of bit pairs being equal to a number of weights for each associated perceptron. The technique also includes associating the TCAM with an array of x-bit saturating counters, and performing a branch prediction for a history vector of a given branch, the branch prediction indicating a perceptron prediction. The technique includes determining a most influential bit location in the history vector, the most influential bit location having a greatest weight of an associated perceptron.