Patents by Inventor James J. C. Lan

James J. C. Lan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for verifying hold time in integrated circuit design
    Patent number: 6023767
    Abstract: A method for verifying proper communication between a first circuit and a second circuit of an electronic device. First it is determined which global clocks the first circuit and the second circuit are timed by. Then, the clock signal is shifted between the first and second storage circuits by an amount equal to or greater than a global clock skew budget of the device if it is determined that the first and second storage circuits are timed by different global clocks. Finally, verifying proper operation of the second circuit against a local clock skew budget of the device is done.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: February 8, 2000
    Assignee: Intel Corporation
    Inventors: Sudarshan Kumar, James J. C. Lan, Rajesh Manglore