Abstract: An arrangement and method of reconfiguring a circuit board and package arrangement employs one-time programmable elements on a package to allow a programmable first package arrangement having a first package board and a first integrated circuit to be readily replaced. The first package arrangement was programmed to operate with a first set of operating parameters. The replacement package arrangement, having a second package board and a second integrated circuit, may be substantially identical to the first package arrangement except programmed to operate with a second set of operating parameters different from the first set of op crating parameters. The replacement of the first package arrangement by the second, differently programmed package arrangement, provides a reconfigured circuit board and package arrangement while avoiding the obsoleting of the circuit board.

Abstract: An integrated circuit package includes at least one one-time programmable element, such as a fuse, having a first end and a second end separated by a programmable link. The programmable element is positioned on a surface other than the top surface, e.g., a side surface or the bottom surface of the package substrate to render them less conspicuous to unscrupulous suppliers intent on tampering with the package. The information programmed by the fuses may relate to speed or voltage ratings for a microprocessor.

Abstract: A process for positioning bond pads around a semiconductor die periphery on an octant basis, taking into account both manufacturing and design limitations. The process positions bond pad centers such that the spacing (pitch) increases towards the die corners. The pitch increase is iteratively calculated from an approximated wire angle. The process iteratively recalculates an octant's pad positions until optimum values are converged upon for the approximated wire angle of the cornermost bond pad and for the furthest allowable position for the cornermost bond pad. Once these optimum values are achieved, the resulting bond pad coordinates are stored in memory or a storage media in a format readable by a layout tool being used to design the die (or package). The resulting file is imported into the layout tool, which uses the stored information to physically position bond pads around the die periphery in the die layout.

Abstract: A semiconductor device (10) has a lead-on-chip (LOC) configuration. Leads (24) of the device have central portions (36) which are electrically coupled to peripheral bond pads (14) by conductive wires (30). Inner portions (38) of the leads extend from the central portions toward centerline A--A for improved adhesion and to provide an internal clamping area (41) which stabilizes the leads during wire bonding. In one embodiment, tie bar (22) of leadframe (16) is used to distribute power across semiconductor chip (12). The leadframe may also include chip alignment features (50) and tape alignment features (52) to align chip (12) and insulating tape (18) to the leadframe, respectively.

Abstract: A semiconductor device (10) has a lead-on-chip (LOC) configuration. Leads (24) of the device have central portions (36) which are electrically coupled to peripheral bond pads (14) by conductive wires (30). Inner portions (38) of the leads extend from the central portions toward centerline A--A for improved adhesion and to provide an internal clamping area (41) which stabilizes the leads during wire bonding. In one embodiment, tie bar (22) of leadframe (16) is used to distribute power across semiconductor chip (12). The leadframe may also include chip alignment features (50) and tape alignment features (52) to align chip (12) and insulating tape (18) to the leadframe, respectively.

Abstract: A semiconductor device having a thin package profile is leadless, thereby minimizing necessary mounting space on a substrate. In one form, a semiconductor device has a semiconductor die electrically coupled to a plurality of conductive leads. Each lead has a first portion, a second portion, and an intermediate portion which separates the first and second portions. A package body encapsulates the semiconductor die and the first and intermediate portions of the leads. The second portions of the leads are exposed on the bottom surface of the package body and are used to electrically access the semiconductor die.

Abstract: A packaged semiconductor device is disclosed having at least two electronic components encapsulated in a single body of standard size and pin-out configuration. In accordance with one embodiment of this invention, two leadframes, having electronic components electrically coupled thereto, are positioned such that the electronic components are in a stacked relationship and the outer portions of the two sets of leads within each leadframe are interdigitated. The configuration enables all components to be accessed independently and minimizes the footprint of the device while maintaining a standard package outline.

Abstract: A method for making a semiconductor device having a heat sink is provided in which an opening through the heat sink enables a vacuum source to be applied to a semiconductor die mounting surface. In one form, a semiconductor die is attached to a mounting surface of a leadframe. The leadframe also has a plurality of leads which are electrically coupled to the semiconductor die. The semiconductor die and portions of the leads are encapsulated in a package body. Also incorporated into the package body is a heat sink. The heat sink has an opening which extends through the heat sink and exposes a portion of the mounting surface of the leadframe. The opening is used to apply a vacuum to the mounting surface during the formation of the package body so that the mounting surface and heat sink are held in close proximity. The closeness provides a good thermal conduction path from the semiconductor die to the ambient, thereby enhancing the thermal dissipation properties of the device.

Abstract: A semiconductor device having a heat sink is provided in which an opening through the heat sink enables a vacuum source to be applied to a semiconductor die mounted surface. In one form, a semiconductor die is attached to a mounting surface of a leadframe. The leadframe also has a plurality of leads which are electrically coupled to the semiconductor die. The semiconductor die and portions of the leads encapsulated in a package body. Also incorporated in the package body is a heat sink. The heat sink has an opening which extends through the heat sink and exposes a portion of the mounting surface of the leadframe. The opening is used to apply a vacuum to the mounting surface during the formation of the package body so that the mounting surface and heat sink are held in close proximity. The closeness provides a good thermal conduction path from the semiconductor die to the ambient, thereby enhancing the thermal dissipation properties of the device.

Abstract: In a TAB bonded semiconductor device, off-chip power and ground distribution is provided by electrically conductive leads spanning across the face of the semiconductor device. Means for supporting at least one TAB lead carrying a power or ground signal across the face of the semiconductor device to an external bonding site is positioned in a central portion of the chip bonding area. In accordance with one embodiment of the invention, a semiconductor device is provided having a plurality of bonding pads arrayed on at least two sides of a face surface thereon. At least one TAB lead is bonded to a bonding pad on a first side of the face surface and spans across the face surface and is bonded to a bonding pad located in a second side of the face surface. An interior tape section overlies a central portion of the face surface supporting the TAB lead.

Abstract: A pad array electronic device for mounting on a substrate, such as a printed circuit board (PCB), has a relatively rigid package body with a plurality of holes bearing connecting mechanisms for bonding to lands on the PCB. The package body may be a thermoset plastic or other material that can be injection molded around an electronic component, such as an integrated circuit (IC) bonded to a lead frame. An integrated circuit die or other electronic component is mounted in proximity with or on the lead frame and electrical connections between the integrated circuit chip and the frame are made by any conventional means. In one aspect, the substrate leads are provided at their outer ends that are exposed by holes in the package with solder balls or pads for making connections to the PCB. The package body may be optionally used to stand off the device a set distance from the PCB so that the solder balls will form the proper concave structure.

Abstract: A lead frame having multiple layers permits fine connection to a large number of bonding pads on an electronic component such as an integrated circuit (IC), but strong external package leads. A fully featured or completely extensive lead frame layer bears proximal ends that may be finely dimensioned for connection with the bonding pads of an IC. A second frame layer is laminated with the first layer, but does not have proximal ends that extend as far as those of the fully featured frame layer. The doubled external leads for mounting to a printed circuit board (PCB) are relatively stronger than the single, more finely featured proximal lead ends that are bonded to the component. The lead frame layers may also differ with respect to their thicknesses, electrical conductivity, strength and solder-wetting characteristics.

Abstract: A molded semiconductor package having a flagless leadframe wherein a semiconductor die is disposed in or above a die opening of a leadframe. This allows for thin, symmetrical packages and packages having a minimum number of material interfaces to be manufactured because no leadframe flags and minimal die bond material are employed. The present invention further includes guard rings to protect high stress areas of the semiconductor die from damage and heat spreaders to more effectively spread heat dissipated by the semiconductor die.