Abstract: The Frame Saver is essentially a brace that is specially designed to reinforce frame stands when they lose their stability. Manufactured of a durable thermoplastic plastic material, this product is a splint-type apparatus, configured to slide directly onto the frame stand at the point of compromise.

Abstract: A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies. The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.

Abstract: A memory includes input/output paths and electrical leads. Each of the input/output paths are coupled to separate electrical leads. The memory is configured to operate in a test architecture and an operating architecture. In the test architecture, logic enables a greatest number of input/output paths. In the operating architecture, the memory enables the same or fewer input/output paths. The method of selecting a configuration includes establishing an operating and a test architecture and testing the memory in its greater input/output configuration.

Abstract: A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies. The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.

Abstract: A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.

Abstract: A semiconductor wafer testing system tests one or more die clusters on a semiconductor wafer, using a test circuit to test multiple sections or areas of each die in parallel. The semiconductor wafer testing system has a buffer connected to the die cluster via the test circuit. The buffer writes test data onto a section of each die in the die cluster. The buffer reads test data from the section of each die in the die cluster.

Abstract: A memory includes input/output paths and electrical leads. Each of the input/output paths are coupled to separate electrical leads. The memory is configured to operate in a test architecture and an operating architecture. In the test architecture, logic enables a greatest number of input/output paths. In the operating architecture, the memory enables the same or fewer input/output paths. The method of selecting a configuration includes establishing an operating and a test architecture and testing the memory in its greater input/output configuration.

Abstract: A semiconductor wafer testing system tests one or more die clusters on a semiconductor wafer, using a test circuit to test multiple sections or areas of each die in parallel. The semiconductor wafer testing system has a buffer connected to the die cluster via the test circuit. The buffer writes test data onto a section of each die in the die cluster. The buffer reads test data from the section of each die in the die cluster.

Abstract: A semiconductor die isolation system electrically disconnects the semiconductor die from a routing mechanism when an isolation block is activated. The semiconductor die is tested through a routing mechanism connection with a testing device on a semiconductor wafer. The isolation block is activated when the testing is completed.

Abstract: A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.

Abstract: An apparatus for mounting a semiconductor device to a circuit board for testing is disclosed. The semiconductor device includes semiconductor circuitry and leads to connect the semiconductor circuitry to the circuit board. Additionally, the semiconductor device is decapped so that at least a portion of the semiconductor circuitry is exposed. The apparatus includes a frame and a fastener. The frame is adapted to mate with the semiconductor device, and forms an opening for accessing the semiconductor circuitry and an edge surface for receiving the semiconductor device. The fastener is connected with the frame for removably connecting the frame to the circuit board. By using a frame instead of a socket, the distance to the semiconductor device once the device is mounted to the circuit board, and particularly the top side of the semiconductor device, can be reduced so that the device may be tested using a probe.

Abstract: An apparatus for mounting a semiconductor device to a circuit board for testing is disclosed. The semiconductor device includes semiconductor circuitry and leads to connect the semiconductor circuitry to the circuit board. Additionally, the semiconductor device is decapped so that at least a portion of the semiconductor circuitry is exposed. The apparatus includes a frame and a fastener. The frame is adapted to mate with the semiconductor device, and forms an opening for accessing the semiconductor circuitry and an edge surface for receiving the semiconductor device. The fastener is connected with the frame for removably connecting the frame to the circuit board. By using a frame instead of a socket, the distance to the semiconductor device once the device is mounted to the circuit board, and particularly the top side of the semiconductor device, can be reduced so that the device may be tested using a probe.