Abstract: A method and system of modeling power leakage for a design comprises providing one or more cell libraries comprising parameters for particular device characteristics and providing a module configured to determine of cell leakages of a device for a PVT corner. In determining the cell leakage, the module uses the device characteristics contained in the one or more cell libraries, in combination with one or more components at a PVT for a predetermined application and an amount of devices in a leakage path (Fckt) and a leakage distribution (Fchip). There is no need to recharacterize the one or more cell libraries.

Abstract: The invention presents a method of accommodating for across chip line variation (ACLV) and/or changing static timing of an integrated circuit design. The invention first establishes a circuit design having initial timing requirements and an initial voltage supply and also establishes a relationship between gate timing variations caused by voltage supply changes and gate timing variations caused by manufacturing processing changes. Then, according to the customer's orders that change the initial timing requirements to revised timing requirements, the invention changes the initial voltage supply to a revised voltage supply to accommodate the revised timing requirements (and ACLV if desired) based on the relationship between voltage limits and transistor delay. This process of changing the initial voltage supply does not alter the circuit design.