Patents by Inventor James J. Freeman

James J. Freeman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10389838
    Abstract: Disclosed are various embodiments for client-side predictive caching of content to facilitate use of the content. If account is likely to commence use of a content item through a client, the client is configured to predictively cache the content item before the use is commenced. In doing so, the client may obtain an initial portion of the content item from another computing device. The client may then initialize various resources to facilitate use of the content item by the client. The client-side cache may be divided into multiple segments with different content selection criteria.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: August 20, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Lei Li, Andrew Jason Ma, Gurpreet Singh Ahluwalia, Abhishek Dubey, Sachin Shah, Vijay Sen, Gregory Scott Benjamin, Prateek Rameshchandra Shah, Cody Wayne Maxwell Powell, Meltem Celikel, Darryl Hudgin, James Marvin Freeman, II, Aaron M. Bromberg, Bryant F. Herron-Patmon, Nush Karmacharya, Joshua B. Barnard, Peter Wei-Chih Chen, Stephen A. Slotnick, Andrew J. Watts, Richard J. Winograd
  • Patent number: 10370448
    Abstract: The present invention is based, in part, on the identification of novel human anti-PD-1, PD-L1, and PD-L2 antibodies. Accordingly, the invention relates to compositions and methods for diagnosing, prognosing, and treating conditions that would benefit from modulating PD-1, PD-1, and/or PD-L2 activity (e.g., persistent infectious diseases autoimmune diseases, asthma, transplant rejection, inflammatory disorders and tumors) using the novel human anti-PD-1, PD-L1, and PD-L2 antibodies described herein.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: August 6, 2019
    Assignees: EMORY UNIVERSITY, DANA-FARBER CANCER INSTITUTE, INC.
    Inventors: Gordon J. Freeman, Rafi Ahmed, Timothy D. Jones, Francis J. Carr, James P. Gregson
  • Publication number: 20190182348
    Abstract: Disclosed are various embodiments for predictive caching of content to facilitate use of the content. If account is likely to commence use of a content item, the content item is cached before the use is commenced. The cache may be divided into multiple segments with different content selection criteria.
    Type: Application
    Filed: February 18, 2019
    Publication date: June 13, 2019
    Inventors: LEI LI, ANDREW JASON MA, GURPREET SINGH AHLUWALIA, ABHISHEK DUBEY, SACHIN SHAH, VIJAY SEN, GREGORY SCOTT BENJAMIN, PRATEEK RAMESHCHANDRA SHAH, CODY WAYNE MAXWELL POWELL, MELTEM CELIKEL, DARRYL HUDGIN, JAMES MARVIN FREEMAN, II, AARON M. BROMBERG, BRYANT F. HERRON-PATMON, NUSH KARMACHARYA, JOSHUA B. BARNARD, PETER WEI-CHIH CHEN, STEPHEN A. SLOTNICK, ANDREW J. WATTS, RICHARD J. WINOGRAD
  • Patent number: 8986537
    Abstract: Provided are multiple correlations for relationships between MI value for a brightstock extract and the distillation cut point temperature used for separation of the vacuum resid that is used to form the brightstock extract. Based on these correlations, a BSE having a desired MI value can be formed based on an adjustment of the distillation cut point temperature. A first correlation establishes a relationship between a fractional weight boiling temperature for a vacuum resid fraction and a distillation cut point temperature for separating the vacuum resid fraction from at least one distillate fraction in a feedstock. A second correlation establishes a relationship between a fractional weight boiling temperature for a brightstock extract derived from the vacuum resid fraction, and the fractional weight boiling temperature for the vacuum resid fraction. A third correlation has been established between the fractional weight boiling temperature for the brightstock extract and a mutagenicity index value.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 24, 2015
    Inventors: Cristina M. Sircar, Keith K. Aldous, James J. Freeman, Katy O. Goyak
  • Patent number: 8857507
    Abstract: A downhole communication system including a plurality of addressed downhole devices, a plurality of remote devices, and a plurality of conductors. Each of the plurality of conductors is electrically conductively connected to at least one of the plurality of addressed downhole devices and at least one of the plurality of remote devices. The downhole communication system is configured such that at least one of the plurality of devices is able to receive and recognize encoded addresses and encoded data in an electrical signal transmitted to at least one of the plurality of conductors electrically conductively isolated from the device configured to be receptive to the electrical signal having the encoded addresses and encoded data.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: October 14, 2014
    Assignee: Baker Hughes Incorporated
    Inventor: James J. Freeman
  • Publication number: 20120086460
    Abstract: A system includes a common line configured to conduct electrical power and one or more monitoring devices coupled to the common line and configured to operate when a positive voltage is provided on the common line. The system also includes a single use device coupled to the common line and an activation circuit coupled between the single use device and the common line, the activation circuit only allowing current to flow through the single use device when a negative voltage is provided on the common line.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 12, 2012
    Applicant: BAKER HUGHES INCORPORATED
    Inventor: James J. Freeman
  • Publication number: 20110146992
    Abstract: This disclosure relates to an apparatus and method for controlling the amount of an additive injected into production fluid in a plurality of production zones. The injection devices may be dynamically controlled such that a central or decentralized control system may instruct a plurality of additive injection assemblies to inject additive, wherein different additive and/or different amounts of additive may be injected in the production fluid in the plurality of production zones. The apparatus includes one or more controllers to send operating commands to downhole regulating elements that may control the amount of additive being injected directly or indirectly.
    Type: Application
    Filed: December 22, 2009
    Publication date: June 23, 2011
    Applicant: Baker Hughes Incorporated
    Inventors: James J. Freeman, Larry G. Schoonover
  • Patent number: 7839148
    Abstract: A method and related system calibrating downhole tools for drift. Some of the illustrative embodiments are a logging tool comprising a tool body, a transmitter antenna associated with the tool body, a transmitter electronics coupled to the transmitter antenna, a first receiver antenna associated with the tool body, a first receiver electronics coupled to the first receiver antenna, and a signal generator separate from the first transmitter electronics, the signal generator coupled to the first receiver electronics, and the first signal generator provides a calibration signal to the first receiver electronics.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: November 23, 2010
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Imran Vehra, James J. Freeman, Christopher A. Golla, Randal T. Beste, Michael S. Bittar
  • Publication number: 20090251960
    Abstract: Disclosed herein are various nonvolatile integrated device embodiments suitable for use at high temperatures. In some embodiments, a high temperature nonvolatile integrated device comprises a sapphire or spinel substrate having multiple ferroelectric memory cells disposed upon it. In other embodiments, a high temperature nonvolatile integrated device comprises a silicon on insulator substrate or a large bandgap semiconductor substrate having multiple ferroelectric or magnetic memory cells disposed on it. In yet other embodiments, a high temperature nonvolatile integrated device comprises a sapphire, silicon on insulator, or a large bandgap substrate having programmable read only memory (PROM) cells or electrically erasable PROM (EEPROM) cells disposed on it.
    Type: Application
    Filed: April 7, 2008
    Publication date: October 8, 2009
    Applicant: Halliburton Energy Services, Inc.
    Inventors: Roger L. Schultz, James J. Freeman
  • Publication number: 20090178804
    Abstract: Disclosed herein is a downhole communication system. The system includes, a plurality of addressed downhole devices, a plurality of remote devices, and a plurality of conductors. Each of the plurality of conductors is electrically conductively connected to at least one of the plurality of addressed downhole devices and at least one of the plurality of remote devices, the downhole communication system is configured such that at least one of the plurality of devices is able to receive and recognize encoded addresses and encoded data in an electrical signal transmitted at least one of the plurality of conductors electrically conductively isolated from the device configured to be receptive to the electrical signal having the encoded addresses and encoded data.
    Type: Application
    Filed: January 10, 2008
    Publication date: July 16, 2009
    Applicant: BAKER HUGHES INCORPORATED
    Inventor: James J. Freeman
  • Patent number: 7442932
    Abstract: High temperature imaging devices are disclosed. In one embodiment, the imaging device comprises an array of photosensitive elements fabricated on an insulator substrate, and an information storage component coupled to the array. The information storage component stores data representing one or more light patterns detected by the array. The light patterns may be images or spectral patterns. The insulator substrate may be a sapphire or spinel substrate. Alternatively, the substrate may be silicon carbide or an insulated silicon substrate. In at least some embodiments, a processor is integrated on the same substrate as the array.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: October 28, 2008
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Roger L. Schultz, James J. Freeman, Neal G. Skinner, Steven G. Streich
  • Patent number: 7307425
    Abstract: A resistivity tool includes receiver electronics near each receiver antenna loop. Placement of the electronics in this position such as at the circuit card between the terminal ends of the receiver antenna loop improves signal to noise ratio by reducing or eliminating interference, noise, and cross-talk of transmissions from the receiver to a remote microprocessor. By using material such as silicon-on-sapphire, electronics can be miniaturized and operate reliably at when exposed to high temperatures, even for long periods.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: December 11, 2007
    Assignee: Halliburton Energy Services, Inc.
    Inventors: James J. Freeman, Imran Vehra, Christopher A. Golla, Sergei Sharonov
  • Patent number: 7301223
    Abstract: In at least some embodiments, electronic devices suitable for use at temperatures in excess of 200 C. may comprise an integrated circuit fabricated on a silicon carbide substrate, and a thick passivation layer. In other embodiments, electronic devices suitable for use at temperatures in excess of 200 C. may comprise an integrated circuit formed from silicon located on a sapphire substrate, and a thick passivation layer. The electronic devices may be implemented in the context of hydrocarbon drilling and production operations.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: November 27, 2007
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Paul F. Rodney, James E. Masino, Christopher A. Golla, Roger L. Schultz, James J. Freeman
  • Patent number: 7017662
    Abstract: In at least some embodiments, a tool may comprise a tool body and one or more tool components. The tool may further comprise tool electronics located within the tool body, wherein the tool electronics are operable to sense and store tool component characteristics and environmental characteristics. At least some of the tool electronics are operable, at least for one week, when exposed to temperatures of at least 200 Celsius. The tool electronics may be integrated circuits formed on a silicon carbide substrate or a silicon on sapphire substrate. One illustrative embodiment of the tool is a drill bit for employment in a high temperature drill well.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: March 28, 2006
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Roger L. Schultz, James J. Freeman, Paul F. Rodney
  • Patent number: 6972556
    Abstract: A system for measuring power of a circuit on a printed circuit board (PCB) including first and second circuits, a power strip, a power plane, and a calibration strip. The power strip is connected to the power plane to the first circuit, is embedded in the PCB during the manufacturing process, and also has at least two vias for measuring a voltage drop. The calibration strip is also embedded in the PCB during the manufacturing process and has at least two vias for measuring a voltage drop. The second circuit is configured to measure a voltage drop across the power strip as a first voltage and a voltage drop across the calibration strip as a second voltage, and to calculate the power being fed to the first circuit based on the first voltage and the second voltage.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: December 6, 2005
    Assignee: Broadcom Corporation
    Inventors: James M. Kronrod, James J. Freeman, Kelly Coffey
  • Patent number: 6861834
    Abstract: A system for measuring power of a circuit on a printed circuit board (PCB) including first and second circuits, a power strip, a power plane, and a calibration strip. The power strip is connected to the power plane to the first circuit, is embedded in the PCB during the manufacturing process, and also has at least two vias for measuring a voltage drop. The calibration strip is also embedded in the PCB during the manufacturing process and has at least two vias for measuring a voltage drop. The second circuit is configured to measure a voltage drop across the power strip as a first voltage and a voltage drop across the calibration strip as a second voltage, and to calculate the power being fed to the first circuit based on the first voltage and the second voltage.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: March 1, 2005
    Assignee: Broadcom Corporation
    Inventors: James M. Kronrod, James J. Freeman, Kelly Coffey
  • Publication number: 20040257063
    Abstract: A system for measuring power of a circuit on a printed circuit board (PCB) including first and second circuits, a power strip, a power plane, and a calibration strip. The power strip is connected to the power plane to the first circuit, is embedded in the PCB during the manufacturing process, and also has at least two vias for measuring a voltage drop. The calibration strip is also embedded in the PCB during the manufacturing process and has at least two vias for measuring a voltage drop. The second circuit is configured to measure a voltage drop across the power strip as a first voltage and a voltage drop across the calibration strip as a second voltage, and to calculate the power being fed to the first circuit based on the first voltage and the second voltage.
    Type: Application
    Filed: July 20, 2004
    Publication date: December 23, 2004
    Applicant: Broadcom Corporation
    Inventors: James M. Kronrod, James J. Freeman, Kelly Coffey
  • Publication number: 20020050827
    Abstract: A system for measuring power of a circuit on a printed circuit board (PCB) including first and second circuits, a power strip, a power plane, and a calibration strip. The power strip is connected to the power plane to the first circuit, is embedded in the PCB during the manufacturing process, and also has at least two vias for measuring a voltage drop. The calibration strip is also embedded in the PCB during the manufacturing process and has at least two vias for measuring a voltage drop. The second circuit is configured to measure a voltage drop across the power strip as a first voltage and a voltage drop across the calibration strip as a second voltage, and to calculate the power being fed to the first circuit based on the first voltage and the second voltage.
    Type: Application
    Filed: June 28, 2001
    Publication date: May 2, 2002
    Applicant: Broadcom Corporation
    Inventors: James M. Kronrod, James J. Freeman, Kelly Coffey
  • Patent number: 4570268
    Abstract: A patient's garment which is suitable for various medical procedures, which will give the patient a sense of dignity and well-being, and which is of relatively low cost, high durability and common sizing. The patient's garment has a body portion (10) and sleeves (14). The body portion includes a main panel (16) which can be positioned to either the front or rear side of the patient and a pair of adjacent side panels (18, 20) which would normally be positioned on the other side of the patient. The outer side edges (28, 30) of the side panels are joined together in overlapping relationship when the garment is worn by the patient by a plurality of vertically spaced apart fasteners (42, 44). The sleeves 14 are sewn to the body portion, and the top of each sleeve is provided with an openable seam having adjacent mating edges (34, 36) which extend from the neck of the patient over the patient's shoulder and down along the arms.
    Type: Grant
    Filed: December 7, 1983
    Date of Patent: February 18, 1986
    Inventor: James J. Freeman
  • Patent number: 4364078
    Abstract: An aluminum over silicon barrier extends over the lateral edges of an integrated circuit chip into adjacent scribe lines forming an edge barrier.
    Type: Grant
    Filed: May 16, 1980
    Date of Patent: December 14, 1982
    Assignee: Synertek
    Inventors: Paul W. Smith, James J. Freeman, Donald D. Forsythe, Megha Shyam, Kenneth K. Yagura, Gunnar Wetlesen
  • Patent number: 4749417
    Abstract: A process for improving the corrosion resistance of an iron or steel part having a phosphate conversion coating, said method comprising contact of said part with a solution containing ions selected from the group of cobalt ions and nickel ions. Preferably, the solution also contains stannous ions. Contact may be by immersion or spraying.
    Type: Grant
    Filed: April 3, 1987
    Date of Patent: June 7, 1988
    Assignee: The Lea Manufacturing Company
    Inventors: James N. Tuttle, Jr., Olyn P. Jaboin