Patents by Inventor James J. Greed, Jr.

James J. Greed, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5677765
    Abstract: A method for calibrating topographic instruments, operating at sub-micrometer resolution levels, includes providing a calibration standard having a known one-dimensional power spectral density function. A roughness is calculated from the known one dimensional power spectral density function in relation to an atomic scale topographic dimension, .increment.z.sub.i. The roughness of the calibration standard is measured by detecting light scattering therefrom and computing an isotropic power spectral density curve over the effective spatial bandwidth of the topographic instrument being calibrated. The measured roughness is then compared against the calculated roughness to determine whether the two values of roughness coincide.
    Type: Grant
    Filed: August 16, 1996
    Date of Patent: October 14, 1997
    Assignee: VLSI Standards, Inc.
    Inventors: Ellen R. Laird, W. Murray Bullis, James J. Greed, Jr., Bradley W. Scheer
  • Patent number: 5599464
    Abstract: A calibration target for topographic inspection instruments, operating at sub-micrometer resolution levels, having features on the order of 10 Angstroms in vertical height, an atomic scale distance. The features are formed on a silicon substrate, such as a wafer, by deposition of a thick oxide, such as a typical thermal oxide, over the wafer surface. A pattern of features is patterned and etched to the level of raw silicon at the wafer surface. Areas which have been etched are converted to a thin oxide, which slightly lowers the level of silicon in these areas. All oxide is removed and the slightly lower level of silicon gives rise to features having atomic scale vertical topographic dimensions. Millions of such features are produced simultaneously on a wafer to mimic the effect of haze or micro-roughness on a polished wafer.
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: February 4, 1997
    Assignee: VLSI Standards, Inc.
    Inventors: Ellen R. Laird, W. Murray Bullis, James J. Greed, Jr., Bradley W. Scheer
  • Patent number: 5453830
    Abstract: A test device for calibrating an optical surface inspection system, such as a pellicle or reticle inspection system, comprising a substrate having raised diffractors with at least one beam-diffracting geometric feature aligned to diffract light directed from an angle of incidence of less than 30.degree. . The beam-diffracting geometric feature is preferably a vertex aligned generally perpendicular to the surface of the substrate. A detection beam which impinges the vertex is diffracted, with diffracted beams being collected by a collector. The raised diffractor thereby simulates a foreign particle on a substrate, allowing calibration of the system. The apparent size of the diffractor and therefore the simulated particle can be varied by varying the vertices or the height of the raised diffractor. If a substrate is to have more than one diffractor, the diffractor should be spaced apart by a distance greater than the diameter of the detection beam.
    Type: Grant
    Filed: June 14, 1994
    Date of Patent: September 26, 1995
    Assignee: VLSI Standards, Inc.
    Inventor: James J. Greed, Jr.