Abstract: A circuit and method for automatically reducing an electrical path length difference between two electromagnetic signal paths. A counter converts the electrical path length difference to a multi-bit digital signal, and each bit in the signal operates a different one of plural switches which selectively inserts a time delay into one of the two electromagnetic signal paths to reduce the electrical path length difference. A comparator determines whether the electrical path length difference exceeds a threshold. The rectified AC component of a phase detector output is fed to the comparator which activates the counter when the threshold is exceeded. The counter drives the switched time delays in a sweeping fashion until the detected error falls below the threshold, whereupon the sweeping action is terminated.