Abstract: A process for discharging a floating gate semiconductor device formed in a semiconductor substrate, the device having a first active region, a second active region, a charge holding region, and a channel between the first and second active regions, the channel having a length defined by a distance below the charge holding region between the first and second active regions. The process comprises the steps of: applying a first positive voltage of about 4-8 volts to the first active region; applying a second voltage in the range of about 0.5-3 volts to the second active region; applying a third voltage in the range of minus 8 volts to the charge holding region; and coupling the substrate to ground. The first active region may comprise either a source or a drain region of a MOSFET, and the second active region may comprise a source region or a drain region of a MOSFET.

Abstract: An improved method for protecting the gate edge and adjacent source region of a semiconductor device is disclosed. In this method, spacers are formed along the gates of one type of transistor to protect the gate edge and adjacent source area during a self-aligned source etch. Spacers of a different width, which may be optimized for different voltage requirements, are formed along the gates of a second type of transistor of the same intergated circuit. This method is particularly applicable in the formation of EPROM, Flash EPROM, EEPROM, or other memory cells in conjunction with periphery devices needing to sustain relatively higher voltages. By decouplng the memory cell requirement from the periphery device requirement, tighter gate spacing and smaller cell size can be achieved.

Abstract: A memory device, such as a flash EEPROM, employs a high energy implantation to form common source line, avoiding the necessity of self-aligned source etch processes. The use of the high energy implantation, and avoiding the etching process, provides for greater cell uniformity, and better V.sub.T distribution.

Abstract: Highly doped short channel NMOS devices with punch-through protection; intrinsic NMOS devices with low threshold voltage; and long channel NMOS and PMOS devices with low body factor; are constructed by providing one or more lightly doped P regions in a semiconductor wafer in which intrinsic and long channel NMOS devices may be constructed, and one or more N wells in the wafer where PMOS devices can be constructed; forming isolation oxide on the wafer before implanting the wafer to inhibit field inversion in N channel (NMOS) devices; masking N regions of the wafer except where long channel PMOS devices will be formed and portions of P regions of the wafer where long channel NMOS devices will be constructed, and optionally masking P regions where either intrinsic NMOS devices or short channel NMOS devices will be formed; and then implanting the wafer to simultaneously provide a field implant below the isolation oxide, adjacent regions where NMOS devices will be formed, as well as optionally providing a deep imp

Abstract: A method of forming and removing spacers used to mask lightly doped drain (LDD) regions in the formation of a field effect transistor (FET) involves depositing a thin oxide layer over the active region of a substrate and a gate structure formed on the active region. A polysilicon film is provided over the oxide and then doped using a POCl.sub.3 dopant. The polysilicon layer is then etched to form spacers at the ends of the gate and the spacers are used to mask lightly doped drain regions in the substrate during the implantation of source and drain regions. After the implant to form the source and drain regions, the device is subjected to a rapid thermal annealing for approximately 20-60 seconds at approximately 900.degree. C. in an inert atmosphere to cure any damage to the oxide layer which occurs during the source/drain implant. Curing the oxide layer reduces the etch rate of the oxide layer for an etchant which is designed to selectively etch the polysilicon spacers faster than it etches the oxide layer.

Abstract: A subatmospheric pressure condenser has an enclosure within which steam is condensed after exhausting from an associated turbine. The enclosure is flexibly connected to the turbine to permit relative movement therebetween. The condenser also has an outer wall which is flexibly connected to the enclosure to define a vacuum balancing chamber therebetween with the outer wall being structurally connected to the turbine for the purpose of reducing the atmospheric pressure force exerted on the turbine's structure by the turbine. The structural connectors between the outer wall and the turbine intersect the enclosure and provide fluid communication therethrough between the turbine's exhaust port and the vacuum balancing chamber. At the intersection between the structural connectors and the enclosure, sleeves are attached to the enclosure in closely spaced surrounding relationship with each of the structural connectors to minimize liquid intrusion therebetween from the enclosure to the vacuum balancing chamber.