Abstract: The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with the associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.

Abstract: A computer system is provided with a memory management unit (MMU) utilizing a translation look-aside buffer (TLB) arrangement. The computer system includes a bus, a unified cache memory, a main memory, a processor, and a memory controller. The TLB is configured for storing code and/or data. The main memory is coupled to the bus. The main memory contains descriptor tables for mapping virtual-to-physical address translations within a virtual memory system. The processor is coupled to the bus and the unified cache memory. The processor is configured to communicate and sequentially move through the main memory to retrieve a line of information from the main memory for storage in the unified cache memory. The cache is configured for storing the most recently retrieved code and data from main memory. The memory controller is coupled between the bus and the main memory.

Abstract: The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with the associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.

Abstract: The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with the associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.

Abstract: A bus bridge device for enabling communication between a first device and a second device, wherein the first device is based on advanced microprocessor bus advanced system bus (ASB) protocol and the second device is based on peripheral component interconnect (PCI) protocol. The bus bridge device includes an ASB protocol interface coupled to the ASB protocol device, and the ASB protocol interface is adapted to transmit a response to and receive a transaction from the ASB protocol device. The bus bridge device also includes a PCI protocol interface coupled to the PCI protocol device, and the PCI protocol interface is adapted to transmit a transaction to and receive a response from the PCI protocol device. The ASB protocol interface is coupled to the PCI protocol interface.

Abstract: The present invention is drawn to a computer implemented method and system for synchronously driving slave responses onto an ASB (advanced system bus) bus. On the one hand, in response to a read transfer from a ASB master, an ASB slave predicts the read transfer to be intended for a device attached to the ASB slave if the device is ready to return read data. On the other hand, in response to a write transfer from the ASB master, the ASB slave predicts the write transfer to be intended for the device attached to the ASB slave. In both scenarios, a device select signal (Dsel) is utilized to validate these two predictions. That is, the read slave response driven by the ASB slave does not enter the ASB bus when the device select signal does not select the ASB slave. Also, the write slave response driven by the ASB slave does not enter the ASB bus when the device select signal does not select the ASB slave.

Abstract: An apparatus is provided for interfacing a processor with a bus of a computer system wherein the processor performs burst read operations in both a sequential and a non-sequential manner and the bus is incapable of supporting burst operations that are non-sequential. The apparatus includes an interface adaptor circuit that is coupled between the processor and the bus. The interface adaptor circuit is operative as a burst order translator between the processor and the bus, and has a bridge configured to connect together the processor and the bus. The bridge is operative to translate processor burst operations into operations supported by the bus. The bridge has a processor interface coupled between the processor and the interface adaptor circuit and a bus interface coupled between the bus and the interface adaptor circuit.

Abstract: The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with the associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.

Abstract: The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.

Abstract: A method and system for cache replacement among configurable cache sets. In one embodiment, the present invention identifies a cache location corresponding to uncached data received from main memory and determines a data type for the uncached data. The present invention then examines the cache location in at least one of the configurable cache sets which is configured for the data type of the uncached data. Provided that the cache location of at least one of the configurable cache sets is not occupied by valid data and that the same configurable cache set is configured for the data type of the uncached data, the present invention stores the uncached data into that configurable cache set at the cache location without displacing valid data therein.

Abstract: The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.

Abstract: The present invention relates to a system and method for supporting DMA I/O devices. A PCI-PCI bridge is provided to support DMA I/O devices on the PCI bus. Through the use of two signal lines and a serial link, DMA transfers may be accomplished over the PCI bus. A PCI-ISA dock bridge is also provided to allow the system to support DMA I/O devices and ISA masters (i.e., any device including DMA I/O devices on the ISA bus that generates ISA cycles) on the ISA bus.

Abstract: The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.

Abstract: A computer system having a multiplex address/data bus with a multiplex system controller and method therefor is disclosed which provides in a computer system having time shared use of a multiplex address/data bus to reduce the number of required pins for devices within the computer system, a CPU having at least one address bus, at least one data bus, at least one memory input/output, and at least one CPU control bus coupled thereto for sending and receiving information.

Abstract: A system for altering a clock frequency to a logic controlling device that controls logic which runs at a fixed frequency slower than a frequency of a computer system running the logic. The system speeds up the clock signal to a logic controller when the logic controller is arbitrating between different operational requests. When the logic controller acknowledges a specific operational request, the clock controller immediately slows the clock signal down in order to allow a command strobe length that the logic device executing a specific operation request requires.

Abstract: The present invention relates to an apparatus and method for supporting DMA I/O devices on a PCI bus. A DMA I/O device is coupled to a DMA controller via a serial link and two signal lines. The serial link is used by the DMA I/O device to request a DMA transfer. When the DMA controller receives the serialized DMA request, it sends a signal to an arbiter and waits for the PCI bus to be granted to the DMA controller for use during the DMA transfer. When granted the PCI bus, the DMA controller signals the DMA I/O device. The DMA I/O device asserts a signal in response to the one asserted by the DMA controller. The DMA controller recognizes the signal asserted by the DMA I/O device and continues with the DMA transfer. The transfer continues for as long as the DMA I/O device continues to assert the signal or for as long as the DMA controller is programmed.

Abstract: An event driven power management control system. The event driven power management control system is compatible with existing CPU power management control units which only monitor CPU activity. The event driven power management control system is able to modify a STPCLK# signal asserted by the CPU power management control unit if external or internal events in the computer system require the CPU to run at full speed in order to service the break event.

Abstract: The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.