Abstract: Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.

Abstract: Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.

Abstract: An integrated circuit (100) includes a firewall input terminal, a first circuit (110, 120, 170, 172), and a second circuit (220). The firewall input terminal is for receiving a firewall input signal. The first circuit (110, 120, 170, 172) is coupled to a first power supply voltage terminal (203) and has an output for providing a control signal. The second circuit is coupled to a second power supply voltage terminal (210), to the firewall input terminal (214), and to the first circuit (110, 120, 170, 172). When the firewall input signal is inactive, an activation of the control signal affects the operation of the second circuit. When the firewall input signal is active, an activation of the control signal does not affect the operation of the second circuit.

Abstract: A cascode logic circuit provides a pair of differential output nodes that are pulled up by a pair of cross-coupled P-channel output transistors. The output nodes are connected to outputs of an N-channel combinatorial network that receives a differential input and functions to connect one of the output nodes to a positive supply and the other to ground, depending upon the differential input, thus providing a push-pull effect. The output nodes may be connected to the differential output of the combinatorial network by source-drain paths of separate N-channel transistors, with the gates of these transistors connected to the positive supply to capacitively isolate the output nodes from the combinatorial network; alternatively, the gates of these transistors may be clocked. A fully static latch is provided by adding cross-coupled N-channel transistors connecting the output nodes to ground, so the low side of the output is held down instead of being allowed to float.