Abstract: A movable barrier operator comprising a motor, communication circuitry configured to receive a control signal and communicate with a door lock associated with a passageway door, and a controller. The controller is configured to authenticate the control signal, wherein authenticating the control signal includes associating the signal with a first level of access or a second level of access. The controller is further configured to communicate with the door lock via the communication circuitry to permit opening of the passageway door in response to associating the control signal with the first level of access and inhibit opening of the passageway door in response to associating the control signal with the second level of access. The controller is configured to cause the motor to open the movable barrier regardless of association of the control signal with the first level of access or the second level of access.

Abstract: A process of repairing a component includes identifying a void in a component; determining at least one approximate physical configuration of the void; inserting borescope into the component in order to view the void; providing a repair rod approximately equivalent to at least one of the least one approximate physical configuration of the void; inserting the repair rod into component; confirming insertion of the repair rod in the void; separating the repair rod to leave a repair plug in the void; and depositing braze paste over the repair plug in the void.

Abstract: A movable barrier operator comprising a motor, communication circuitry configured to receive a control signal and communicate with a door lock associated with a passageway door, and a controller. The controller is configured to authenticate the control signal, wherein authenticating the control signal includes associating the signal with a first level of access or a second level of access. The controller is further configured to communicate with the door lock via the communication circuitry to permit opening of the passageway door in response to associating the control signal with the first level of access and inhibit opening of the passageway door in response to associating the control signal with the second level of access. The controller is configured to cause the motor to open the movable barrier regardless of association of the control signal with the first level of access or the second level of access.

Abstract: An additive manufacturing system includes an additive manufacturing unit that includes a housing for additively processing a powder material along a build direction into a build assembly. The additive manufacturing system further includes a rotator assembly for rotating the build assembly within the housing. The rotator assembly includes a frame including a first frame arm and a second frame arm and a carriage rotatably coupled to the first frame arm and to the second frame arm. The carriage includes at least one coupling mechanism for removably coupling the carriage to the build assembly. The rotator assembly further includes a drive assembly coupled to the carriage for selectively rotating the carriage about a rotational axis that is generally perpendicular to the build direction.

Abstract: A virtual presence system and method integrates multiple virtual presence technologies, including the ability to enable a user to experience a remote location through a plurality of different types of virtual presence devices. The different types of virtual presence devices might include virtual presence robots, as well drones, land vehicles, devices arranged to be worn by a human, and other virtual presence devices, all of which are accessible through a single website hosted on a server that provides links to the different types of virtual presence devices at selectable locations through a hierarchical query database that stores geographic coordinates, types, and features of the virtual presence devices, GIS to analyze and display geographic information, and communication methods, together with IP addresses and/or aliases that enable the devices to be accessed and controlled.

Abstract: A process of repairing a component includes identifying a void in a component; determining at least one approximate physical configuration of the void; inserting borescope into the component in order to view the void; providing a repair rod approximately equivalent to at least one of the least one approximate physical configuration of the void; inserting the repair rod into component; confirming insertion of the repair rod in the void; separating the repair rod to leave a repair plug in the void; and depositing braze paste over the repair plug in the void.

Abstract: An additive manufacturing (AM) system includes a build chamber, a base adjustably coupled to the build chamber, and a build material applicator for depositing a build material above a build platform for creating the object. The build platform includes a fixed region fixedly and rigidly coupled to the base and a flex region configured to flex relative to the base in response to a force applied to the build platform by an object. The partial flexibility allows deformation caused by thermal distortion of the build platform during use to reduce final object stress. The AM system can produce larger additively manufactured objects out of crack-prone material. In addition, the partial flexibility may prevent damage to the build platform and/or base without an overly complicated arrangement.

Abstract: A process of repairing a component includes identifying a void in a component; determining at least one approximate physical configuration of the void; inserting borescope into the component in order to view the void; providing a repair rod approximately equivalent to at least one of the least one approximate physical configuration of the void; inserting the repair rod into component; confirming insertion of the repair rod in the void; separating the repair rod to leave a repair plug in the void; and depositing braze paste over the repair plug in the void.

Abstract: Methods and systems are disclosed for transferring data using descriptors to reference memory locations at which data is to be written to or read from. Each descriptor references a respective linked list of descriptor blocks. Each of the descriptor blocks includes a contiguous portion of the memory that stores a plurality of addresses, at which data is to be written to or read from. In response to receiving the data transfer request, a set of data is transferred from a first set of addresses specified in a first descriptor to a second set of addresses specified in a second descriptor by traversing the linked lists of descriptor blocks in the first and second descriptors.

Abstract: In an example, a circuit to manage memory between a first and second microprocessors each of which is coupled to a control circuit, includes: first and second memory circuits; and a switch circuit coupled to the first and second memory circuits, and memory interfaces of the first and second microprocessors, the switch circuit having a mode signal as input. The switch is configured to selectively operate in one of a first mode or a second mode based on the mode signal such that, in the first mode, the switch circuit couples the first memory circuit to the memory interface of the first microprocessor and the second memory circuit to the memory interface of the second microprocessor and, in the second mode, the switch circuit selectively couples the first or second memory circuits to the memory interface of either the first or second microprocessor.

Abstract: Circuits and methods are disclosed that allow devices to control the flow of DMA transfers to or from the devices using a token based protocol. In one example implementation, a DMA circuit includes a transfer control circuit that performs data transfers over a first data channel of a device, when transactions on the first data channel are enabled. The DMA circuit includes a flow control circuit that increments a token count for a data channel of a device when a token for the data channel is received and decrements the token count for each data transfer on the data channel performed by the DMA circuit. The flow control circuit enables data transfers on the data channel when the token count is greater than 0, and otherwise, disables data transfers on the data channel.

Abstract: In approaches for correction of errors introduced in an interconnect circuit, an ECC proxy circuit is coupled between a first interconnect and the second interconnect, and generates for each of the write transactions from a bus master circuit, a first ECC from and associated with data of the write transaction, and transmits the write transaction and associated first ECC on the second interconnect. The ECC proxy circuit also supplements each of the read transactions from the bus master circuit with a reference to a second ECC associated with data referenced by the read transaction. The ECC proxy circuit transmits the read transaction that references the second ECC on the second interconnect. At least one random access memory (RAM) is coupled to the ECC proxy circuit through the second interconnect. The RAM stores data of each write transaction and the first ECC.

Abstract: A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed.

Abstract: In an example, a circuit to manage memory between a first and second microprocessors each of which is coupled to a control circuit, includes: first and second memory circuits; and a switch circuit coupled to the first and second memory circuits, and memory interfaces of the first and second microprocessors, the switch circuit having a mode signal as input. The switch is configured to selectively operate in one of a first mode or a second mode based on the mode signal such that, in the first mode, the switch circuit couples the first memory circuit to the memory interface of the first microprocessor and the second memory circuit to the memory interface of the second microprocessor and, in the second mode, the switch circuit selectively couples the first or second memory circuits to the memory interface of either the first or second microprocessor.

Abstract: A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed.

Abstract: In one embodiment, a method for implementing quality of service (QOS) processing in a data bus interface. Each input read/write command is stored in a first-in-first-out queue. Each input read/write command includes a respective QOS value. In response to an input first read/write command having a QOS value higher than the QOS value of the read/write command at a head of the first-in-first-out queue, the QOS value of each of a first number of read/write commands is increased as each read/write command is removed from the head of the first-in-first-out queue.

Abstract: A water treatment system for producing a sodium hypochlorite solution to control bacteria levels in well water containing: a pH adjuster; a container containing solid calcium hypochlorite for producing a calcium hypochlorite solution; and a container containing solid sodium carbonate for producing the sodium hypochlorite solution and a method of controlling bacteria levels in well water by using intermittent injections of a sodium hypochlorite solution with alternating pH values.

Abstract: A data bus interface channel controller circuit for an N-bit data bus is described. A FIFO command queue is coupled to receive and buffer one or more commands formatted for M-bit transactions. A FIFO data queue is coupled to receive and buffer N-bit formatted data packets. A first translation circuit is coupled to the FIFO command queue and configured to translate the each commands into a selected one of a plurality of transaction formats. A transmission control circuit is coupled and configured to receive and transmit commands removed from the FIFO command queue. The transmission control circuit is configured to track a number of outstanding transmitted commands and, in response to receiving a command having a transaction format different from the previously received command, delay transmission of commands on the N-bit data bus until the number of outstanding transmitted commands equals zero.

Abstract: A hardwired core is embedded in an integrated circuit having programmable circuitry. The hardwired core has a microprocessor; a crossbar interconnect coupled to processor local buses of the microprocessor; and a memory controller interface coupled to the crossbar interconnect. The crossbar interconnect provides pipelines for coupling the hardwired core to the programmable circuitry. The microprocessor, the crossbar interconnect, and the memory controller interface are all capable of operating at a first frequency of operation, and the memory controller interface is further capable of being set to operate at a second frequency of operation having an integer ratio with respect to the first frequency of operation. The crossbar interconnect is configured to direct transactions initiated by the microprocessor to the memory controller interface for accessing one or more memory devices coupled to the memory controller interface via a memory controller.

Abstract: A direct memory access engine is described. The direct memory access engine has a transmit channel coupled to a transmit interface, a receive channel coupled to a receive interface, an arbiter coupled to both the transmit channel and the receive channel, and a set of queues coupled to the arbiter. The set of queues has command buffers, transmit buffers, and receive buffers. A direct memory access-to-processor bus interface is coupled to the set of queues. The transmit buffers are for first separate read and write requests. The receive buffers are for second separate read and write requests which are independent of the first separate read and write requests.