Patents by Inventor James J. Quinlivan
James J. Quinlivan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8709887Abstract: A method of fabricating a gate dielectric layer. The method includes: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.Type: GrantFiled: July 16, 2007Date of Patent: April 29, 2014Assignee: International Business Machines CorporationInventors: Jay S. Burnham, James S. Nakos, James J. Quinlivan, Bernie Roque, Jr., Steven M. Shank, Beth A. Ward
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Publication number: 20100187614Abstract: A method of fabricating a semiconductor structure. The method includes forming a first feature of a first active device and a second feature of a second active device, introducing a first amount of nitrogen into the first feature of the first active device, and introducing a second amount of nitrogen into the second feature of the second active device, the second amount of nitrogen being different from the first amount of nitrogen.Type: ApplicationFiled: April 1, 2010Publication date: July 29, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jay S. BURNHAM, John J. ELLIS-MONAGHAN, James S. NAKOS, James J. QUINLIVAN
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Patent number: 7759260Abstract: A method of fabricating a semiconductor structure. The method includes forming a first feature of a first active device and a second feature of a second active device, introducing a first amount of nitrogen into the first feature of the first active device, and introducing a second amount of nitrogen into the second feature of the second active device, the second amount of nitrogen being different from the first amount of nitrogen.Type: GrantFiled: August 16, 2006Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Jay S Burnham, John J Ellis-Monaghan, James S Nakos, James J Quinlivan
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Patent number: 7714366Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size may be directed to maximize dopant activation in the polysilicon near the gate dielectric and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. A region of polycrystalline silicon may have a varying grain size as a function of a distance measured from a surface of the dielectric film.Type: GrantFiled: November 16, 2004Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles, James J. Quinlivan, Samuel C. Ramac, Michael B. Rice, Beth A. Ward
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Patent number: 7291568Abstract: A method of fabricating a gate dielectric layer, including: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.Type: GrantFiled: August 26, 2003Date of Patent: November 6, 2007Assignee: International Business Machines CorporationInventors: Jay S. Burnham, James S. Nakos, James J. Quinlivan, Bernie A. Roque, Jr., Steven M. Shank, Beth A. Ward
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Patent number: 7138691Abstract: A semiconductor structure includes thin gate dielectrics that have been selectively nitrogen enriched. The amount of nitrogen introduced is sufficient to reduce or prevent gate leakage and dopant penetration, without appreciably degrading device performance. A lower concentration of nitrogen is introduced into pFET gate dielectrics than into nFET gate dielectrics. Nitridation may be accomplished selectively by various techniques, including rapid thermal nitridation (RTN), furnace nitridation, remote plasma nitridation (RPN), decoupled plasma nitridation (DPN), well implantation and/or polysilicon implantation.Type: GrantFiled: January 22, 2004Date of Patent: November 21, 2006Assignee: International Business Machines CorporationInventors: Jay S. Burnham, John J. Ellis-Monaghan, James S. Nakos, James J. Quinlivan
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Patent number: 7109559Abstract: A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.Type: GrantFiled: November 5, 2004Date of Patent: September 19, 2006Assignee: International Business Machines CorporationInventors: Mukesh V. Khare, Christopher P. D'Emic, Thomas T. Hwang, Paul C. Jamison, James J. Quinlivan, Beth A. Ward
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Patent number: 6967167Abstract: A method for removing silicon dioxide residuals is disclosed. The method includes reacting a portion of a silicon dioxide layer (i.e., oxide) to form a reaction product layer, removing the reaction product layer and annealing in an environment to remove oxide residuals. The method finds application in a variety of semiconductor fabrication processes including, for example, fabrication of a vertical HBT or silicon-to-silicon interface without an oxide interface.Type: GrantFiled: September 30, 2003Date of Patent: November 22, 2005Assignee: International Business Machines CorporationInventors: Peter J. Geiss, Alvin J. Joseph, Xuefeng Liu, James S. Nakos, James J. Quinlivan
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Patent number: 6909157Abstract: Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.Type: GrantFiled: September 2, 2003Date of Patent: June 21, 2005Assignee: International Business Machines CorporationInventors: Jay S. Burnham, James S. Nakos, James J. Quinlivan, Steven M. Shank, Deborah A. Tucker, Beth A. Ward
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Patent number: 6893979Abstract: A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.Type: GrantFiled: March 15, 2001Date of Patent: May 17, 2005Assignee: International Business Machines CorporationInventors: Mukesh V. Khare, Christopher P. D'Emic, Thomas T. Hwang, Paul C. Jamison, James J. Quinlivan, Beth A. Ward
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Patent number: 6893948Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.Type: GrantFiled: July 11, 2003Date of Patent: May 17, 2005Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles, James J. Quinlivan, Samuel C. Ramac, Michael B. Rice, Beth A. Ward
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Patent number: 6706644Abstract: Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.Type: GrantFiled: July 26, 2002Date of Patent: March 16, 2004Assignee: International Business Machines CorporationInventors: Jay S. Burnham, James S. Nakos, James J. Quinlivan, Steven M. Shank, Deborah A. Tucker, Beth A. Ward
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Publication number: 20040023476Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.Type: ApplicationFiled: July 11, 2003Publication date: February 5, 2004Applicant: International Business MachinesInventors: Arne W. Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles, James J. Quinlivan, Samuel C. Ramac, Michael B. Rice, Beth A. Ward
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Publication number: 20040018688Abstract: Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrided layer to an additional NO anneal process increases the uniformity of the nitrided layer.Type: ApplicationFiled: July 26, 2002Publication date: January 29, 2004Applicant: International Business Machines CorporationInventors: Jay S. Burnham, James S. Nakos, James J. Quinlivan, Steven M. Shank, Deborah A. Tucker, Beth A. Ward
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Patent number: 6670263Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.Type: GrantFiled: March 10, 2001Date of Patent: December 30, 2003Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles, James J. Quinlivan, Samuel C. Ramac, Michael B. Rice, Beth A. Ward
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Publication number: 20020149064Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.Type: ApplicationFiled: March 10, 2001Publication date: October 17, 2002Inventors: Arne W. Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glenn L. Miles, James J. Quinlivan, Samuel C. Ramac, Michael B. Rice, Beth A. Ward
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Publication number: 20020106906Abstract: A structure comprising a trench having a liner with rounded corners in the top and bottom of the trench is obtained by rapid thermal oxidation.Type: ApplicationFiled: December 13, 2000Publication date: August 8, 2002Applicant: International Business Machines CorporationInventors: Arne W. Ballantine, Jeffrey S. Brown, Jeffrey D. Gilbert, James J. Quinlivan, James A. Slinkman, Anthony C. Speranza
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Patent number: 6417070Abstract: A structure comprising a trench having a liner with rounded corners in the top and bottom of the trench is obtained by rapid thermal oxidation.Type: GrantFiled: December 13, 2000Date of Patent: July 9, 2002Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Jeffrey S. Brown, Jeffrey D. Gilbert, James J. Quinlivan, James A. Slinkman, Anthony C. Speranza