Abstract: Algorithms, examples, and related technology for automatic vectorization of a particular class of loops is described. The loops, denoted “CMMSR loops”, operate to find an extremum and also utilize an index denoting the position of the extremum in an array or other multi-element input. CMMSR loops are identified in a language translator by matching a specified template or having a specified set of parsing results, or both. Generated vectorization code includes, for example, code to compute candidates for the extremum, code to select the same instance of the extremum as a scalar execution when the input contains multiple instances, and wind-down code to compute an index expression based on the selected instance of the extremum. Vectorizations may execute on SIMD hardware or other vector processors.

Abstract: As a memory usage optimization, a compiler identifies coroutines whose activation frames can be allocated on a caller's stack instead of allocating the frame on the heap. For example, when the compiler determines that a coroutine C's life cannot extend beyond the life of the routine R that first calls the coroutine C, the compiler generates code to allocate the activation frame for C on the stack of R, instead of generating code to allocate C's frame from heap memory. In some cases, as another optimization, code for coroutine C is also inlined with code for the routine R that calls C. Coroutine activation frame content variations and layout variations are also described.

Abstract: Algorithms, examples, and related technology for automatic vectorization of a particular class of loops is described. The loops, denoted “CMMSR loops”, operate to find an extremum and also utilize an index denoting the position of the extremum in an array or other multi-element input. CMMSR loops are identified in a language translator by matching a specified template or having a specified set of parsing results, or both. Generated vectorization code includes, for example, code to compute candidates for the extremum, code to select the same instance of the extremum as a scalar execution when the input contains multiple instances, and wind-down code to compute an index expression based on the selected instance of the extremum. Vectorizations may execute on SIMD hardware or other vector processors.

Abstract: A compiler-created cache contains target addresses of multiple indirect routine call sites. Ordinals assigned to indirect routine call sites are used with hardcoded offsets into the cache. Ordinals may be computed using a routine counter and an indirect call site counter. At runtime a target address of an indirect routine call site is compared to an entry in the cache using the hardcoded offset for efficiency. If the target address matches the cache entry, then a redundant call is avoided; otherwise, the call is not redundant, and the cache is updated. The call tested for redundancy may be a security check for malware, or a computationally expensive routine which calculates a return value without any side effects. Stack pointer validity may be checked. The cache may be guarded with code for trustworthy computing. Tail merging may be performed.

Abstract: As a memory usage optimization, a compiler identifies coroutines whose activation frames can be allocated on a caller's stack instead of allocating the frame on the heap. For example, when the compiler determines that a coroutine C's life cannot extend beyond the life of the routine R that first calls the coroutine C, the compiler generates code to allocate the activation frame for C on the stack of R, instead of generating code to allocate C's frame from heap memory. In some cases, as another optimization, code for coroutine C is also inlined with code for the routine R that calls C. Coroutine activation frame content variations and layout variations are also described.

Abstract: A compiler-created cache contains target addresses of multiple indirect routine call sites. Ordinals assigned to indirect routine call sites are used to hardcoded offsets into the cache. Ordinals may be computed using a routine counter and an indirect call site counter. At runtime a target address of an indirect routine call site is compared to an entry in the cache using the hardcoded offset for efficiency. If the target address matches the cache entry, then a redundant call is avoided; otherwise, the call is not redundant, and the cache is updated. The call tested for redundancy may be a security check for malware, or a computationally expensive routine which calculates a return value without any side effects. Stack pointer validity may be checked. The cache may be guarded with code for trustworthy computing. Tail merging may be performed.

Abstract: In an exemplary media implementation, one or more electronically-accessible media include electronically-executable instructions that utilize an application programming interface, the application programming interface facilitating creation of callback-type dynamic function tables; each callback-type dynamic function table including a begin address, an end address, and a callback function, each callback-type dynamic function table corresponding to a code heap that stores code for multiple functions in a runtime environment; wherein interaction between the runtime environment and an operating system is precipitated upon calling the callback function to acquire exception handling and/or unwind information. In another exemplary media implementation, one or more electronically-accessible media include at least part of an operating system that is configured to request from a runtime environment exception handling and/or unwinding information for functions that are managed by the runtime environment.

Abstract: A compiler that forms an intermediate representation of a program using a flow graph with less than all possible edges used to model asynchronous transfers within the program. The flow graph is formed in multiple phases. In one phase, the flow graph is formed without modeling asynchronous transfers. In later phases, representations of the effects of the asynchronous transfers are selectively added. As part of the later phases, edges modeling a possible asynchronous transfer are added to the flow graph following definitions in protected regions of variables that are live outside the protected region. A modified definition of live-ness of a variable is used to incorporate use of the variable in any region, including the protected region, following an asynchronous transfer. Edges from the protected region are also added to the model if the only use of the defined variable is in a handler.

Abstract: A compiler that forms an intermediate representation of a program using a flow graph with less than all possible edges used to model asynchronous transfers within the program. The flow graph is formed in multiple phases. In one phase, the flow graph is formed without modeling asynchronous transfers. In later phases, representations of the effects of the asynchronous transfers are selectively added. As part of the later phases, edges modeling a possible asynchronous transfer are added to the flow graph following definitions in protected regions of variables that are live outside the protected region. A modified definition of live-ness of a variable is used to incorporate use of the variable in any region, including the protected region, following an asynchronous transfer. Edges from the protected region are also added to the model if the only use of the defined variable is in a handler.

Abstract: The construction of Static Single Assignment form (SSA) is used as a dynamic conflict graph so that while constructing SSA in linear time, the program being analyzed is simultaneously register allocated. When allocating a register for the symbol, the conflict set is examined so that the register chosen for the symbol is not used by a symbol in the conflict set. When a symbol is register-allocated, the symbol is added to all the conflict set of all live symbols. A live symbol is determined by keeping two counters, called herein a use counter and a use threshold counter. Both counters are initialized when a definition of a symbol is encountered in a block. Both counters are incremented when a use of the symbol is encountered when traversing a block in a depth-first downward traversal. The use count is decremented when a use is detected when traversing the block in an upward traversal.

Abstract: In an exemplary media implementation, one or more electronically-accessible media include electronically-executable instructions that utilize an application programming interface, the application programming interface facilitating creation of callback-type dynamic function tables; each callback-type dynamic function table including a begin address, an end address, and a callback function, each callback-type dynamic function table corresponding to a code heap that stores code for multiple functions in a runtime environment; wherein interaction between the runtime environment and an operating system is precipitated upon calling the callback function to acquire exception handling and/or unwind information. In another exemplary media implementation, one or more electronically-accessible media include at least part of an operating system that is configured to request from a runtime environment exception handling and/or unwinding information for functions that are managed by the runtime environment.

Abstract: A developer's system compiles a source-language program by parsing it into an intermediate language (IL) program that is independent of the architecture or resources of any particular processor. This system generates a set of machine independent annotations that record attributes and structure of the IL program such as variable definitions and uses. The annotations are in the form of a unique graph structure. Further annotations are used to associate the machine specific optimization information with each of many different microprocessors. The IL program and all the annotations are distributed to multiple user systems having mutually different virtual machines that translate the IL program into object language for their respective different processors. Optimizers in the virtual machines select graph edges based on the machine specific annotations to generate an optimized object program. The translators are table-driven.

Abstract: Disclosed is a masking technique for a SIMD processor (10) which is capable of masking a plurality of individual machine operations within a single instruction incorporating a plurality of operations. To accomplish this each different machine operation within the instruction includes a number of masking bits which address a specific location in a mask register (60). The mask register (60) includes a mask bit bank (62). The mask location selected within the mask register (60) is bit-wise ANDed with a mask context bit (66) in order to establish whether the processing element will be enabled or disabled for a particular conditional sub-routine which is called. One of the bit locations in the mask bit bank (60) is a hard-wired unconditional bit which overrides the mask context bit (66) in order to enable the processing elements in special situations. In addition, a scalar mask bit is provided to facilitate scalar processing.

Abstract: A processing element (42) design is provided for improving performance and reducing the number (30') of memory ports by eliminating the dedication of ports to specific functional units (22, 24, 26, 28) and by providing data paths (46, 48, 50, 52) to other forward results from functional unit outputs directly to other functional unit inputs.