Abstract: A method and system are disclosed for spreading the power associated with digital signals being transmitted to reduce electromagnetic interference (EMI) emissions by receiving, via a first transmission line, a first power spread signal representative a first digital signal modified using a first power spreading digital noise signal, modifying the power spread signal using a second power spreading digital noise signal substantially similar to the first power spreading digital noise signal to generate a second digital signal substantially similar to the first digital signal, modifying the second digital signal using a third power spreading digital noise signal to generate a second power spread signal and providing the second power spread signal for output to a second transmission line.

Abstract: A method and system is disclosed for spreading the power associated with digital signals being transmitted to reduce electromagnetic interference (EMI) emissions by receiving, via a first transmission line, a first power spread signal representative a first digital signal modified using a first power spreading digital noise signal, modifying the power spread signal using a second power spreading digital noise signal substantially similar to the first power spreading digital noise signal to generate a second digital signal substantially similar to the first digital signal, modifying the second digital signal using a third power spreading digital noise signal to generate a second power spread signal and providing the second power spread signal for output to a second transmission line.

Abstract: In response to a software instruction, a static microprocessor is placed in a low current mode by disabling clock pulse generation. Means are provided for disabling a master oscillator when a STOP instruction is decoded. Additional means are provided for inhibiting clock pulses when a WAIT instruction is decoded without disabling the master oscillator. Clock pulse generation is again enabled upon receipt of a reset or interrupt signal.

Abstract: A gate array which has power bus routing for increasing current availability to a plurality of transistor cells is provided. The gate array also has separate power busses for input/internal logic and output circuits. The gate array comprises n columns of transistor cells with two power busses extending substantially along each column to power the cells. Input/internal logic power busses and separate output power busses extend around the perimeter of the columns of transistor cells. At least one power strip for increasing current availability to the transistor cells is routed across the transistor cells substantially perpendicular to the n columns and is connected to both the power busses of each column and to the input/internal logic power busses.

Abstract: A CMOS power on reset circuit is provided which operates with low power supply voltages and yet uses a minimum amount of DC power. The circuit includes a threshold detector which provides an output when the power supply voltage exceeds the transistor threshold voltage by approximately half a volt. A capacitor is connected to the positive power supply terminal to avoid having a narrow output pulse when the power supply rises at a low rate. An output buffer/inverter can be used to provide a better output pulse and to provide a desired output polarity.

Abstract: A CMOS decoder capable of providing a one of n, a two of n, or a three of n decoded output, where n is equal to the number of outputs of the decoder and is a function of the number of bits in a digital signal to be decoded. A first plurality of transistors are used to precharge each of the decoder's outputs to a first voltage potential. A second plurality of transistors are placed in series between the first node and each of the outputs. The second plurality of transistors are controlled by the coded digital signal that is being decoded. The number of decoded outputs can be varied by connecting some of the outputs to some of the transistors of the second plurality of transistors or by connecting others of the outputs to junctions formed by the series placed transistors. In a preferred embodiment, a pair of back-to-back inverters are connected to each of the outputs to provide a static decoder.

Abstract: A CMOS digital decoder has a plurality of circuits having first and second output nodes. A first transistor is used to precharge the first output node and a second transistor is used to precharge the second output node. A third transistor responsive to an enable signal is used to enable the decoder. A fourth transistor is coupled between the third transistor and the first output node and a fifth transistor is coupled between the third transistor and the second output node. A plurality of transistors can be in series between the fourth transistor and the third transistor, or the plurality of transistors can be in parallel between the first and second output nodes depending upon the type of decoder output desired. The decoder can be made a static decoder by coupling a pair of back-to-back inverters to each of the output nodes.

Abstract: A read-only-memory is provided on a semiconductor chip having a reduced number of power supply lines. The memory has a plurality of storage cells arranged in an array. Vertical lines define columns of the memory. Every other vertical line is coupled to a first node. The first node is controllably coupled to a first voltage potential to controllably precharge the first node. The vertical lines not connected to the first node are connected to an output node. P channel field effect transistors are used to couple the vertical lines to the first node and to the output node. A plurality of N-channel field effect transistors controllably couple the vertical lines to a second voltage potential. A vertical line on one side of the column of memory cells is used to provide a precharge voltage to the cell while a vertical line on the other side of the column of memory cells is used to conduct stored information from the cell to the output node.