Abstract: The present invention discloses a system for improving power management for spatial power combining systems, such as a quasi optical grid array amplifier. One aspect of the invention includes the provision of a patterned conductor on the surface the semiconductor chip that opposes the surface upon which the active devices are disposed. This metal material can be used to both enhance heat removal from the chip and to provide a new and more efficient DC biasing path (with the use of vias) for the active components on the other (front) surface of the chip. Another aspect of the invention is the introduction of a dielectric superstrate that attaches to the front surface of the chip to provide an alternative or complementary heat removal and/or biasing structure to the conventional substrate that is typically attached to the back side of the chip. Various combinations of the above features are disclosed.

Abstract: A circuit protection device for protection of sensitive components during high energy radiation sterilization that includes a support substrate and a protective housing. The substrate supports the sensitive components. The protective housing is hermetically coupled to the support substrate to seal the sensitive components within the protective housing. Preferably, the protective housing stops high energy used in the high energy sterilization from damaging the sensitive components from a predetermined exposure level of high energy sterilization. The circuit protection device may further include a protective conductor that is coupled to the support substrate on a side which is opposite the protective housing to prevent high energy from entering the opposite side of the support substrate.

Abstract: The present invention discloses a system for integrating a quasi-optical reflection-mode array into a wave-guiding enclosure. The system includes a quasi-optical reflection mode array and a waveguide assembly that encloses and mounts therein the array. In one preferred embodiment, the waveguide assembly includes an array mounting section into which the array is mounted, a first energy coupling section, a second energy coupling section and a three-port waveguide section. The wave-guiding section has a first port connected to the first energy coupling section, a second port connected to the second energy coupling section, and a third port connected to the array mounting section.

Abstract: The present invention discloses a system for improving power management for a class of spatial power combiners, called active loop probes, or, active loops. One aspect of the invention includes the provision of a patterned conductor on the surface the semiconductor chip that opposes the surface upon which the active devices of the loop are disposed. This metal material can be used to both enhance heat removal from the chip and to provide a new and more efficient DC biasing path (with the use of vias) for the active components on the other (front) surface of the chip. Another aspect of the invention is the introduction of a dielectric superstrate that attaches to the front surface of the chip to provide an alternative or complementary heat removal and/or biasing structure to the conventional substrate that is typically attached to the back side of the chip. Various combinations of the above features are disclosed.

Abstract: The present invention discloses a system for improving power management for spatial power combining systems, such as a quasi optical grid array amplifier. One aspect of the invention includes the provision of a patterned conductor on the surface the semiconductor chip that opposes the surface upon which the active devices are disposed. This metal material can be used to both enhance heat removal from the chip and to provide a new and more efficient DC biasing path (with the use of vias) for the active components on the other (front) surface of the chip. Another aspect of the invention is the introduction of a dielectric superstrate that attaches to the front surface of the chip to provide an alternative or complementary heat removal and/or biasing structure to the conventional substrate that is typically attached to the back side of the chip. Various combinations of the above features are disclosed.

Abstract: A circuit protection device for protection of sensitive components during high energy radiation sterilization that includes a support substrate and a protective housing. The substrate supports the sensitive components. The protective housing is hermetically coupled to the support substrate to seal the sensitive components within the protective housing. Preferably, the protective housing stops high energy used in the high energy sterilization from damaging the sensitive components from a predetermined exposure level of high energy sterilization. The circuit protection device may further include a protective conductor that is coupled to the support substrate on a side which is opposite the protective housing to prevent high energy from entering the opposite side of the support substrate.

Abstract: A circuit protection device for protection of sensitive components during high energy radiation sterilization that includes a support substrate and a protective housing. The substrate supports the sensitive components. The protective housing is hermetically coupled to the support substrate to seal the sensitive components within the protective housing. Preferably, the protective housing stops high energy used in the high energy sterilization from damaging the sensitive components from a predetermined exposure level of high energy sterilization. The circuit protection device may further include a protective conductor that is coupled to the support substrate on a side which is opposite the protective housing to prevent high energy from entering the opposite side of the support substrate.

Abstract: The present invention discloses active unit cell topologies for quasi-optic grid array structures that make use of combinations of one of several broadband or frequency-selective positive (or regenerative) feedback networks, as well as multiple transistor configurations in order to enhance the gain of the grid array amplifier. These new topologies yield higher gain, extending the utility of the grid array amplifier to both new applications requiring higher gain, as well as to higher frequencies where the intrinsic gain of the active devices is lower. They also offer greater flexibility in impedance matching, improving the bandwidth and manufacturability of the design.

Abstract: The present invention discloses a system for integrating a quasi-optical reflection-mode array into a wave-guiding enclosure. The system includes a quasi-optical reflection mode array and a waveguide assembly that encloses and mounts therein the array. In one preferred embodiment, the waveguide assembly includes an array mounting section into which the array is mounted, a first energy coupling section, a second energy coupling section and a three-port waveguide section. The wave-guiding section has a first port connected to the first energy coupling section, a second port connected to the second energy coupling section, and a third port connected to the array mounting section.

Abstract: The present invention discloses an electronically frequency tunable and phase modulatable quasi-optic grid oscillator. The oscillator includes a reference signal input port whereby a small external reference signal is introduced that entrains the frequency and phase of the oscillator signal to it. Amplitude modulation techniques are introduced to further enhance the utility of the oscillator as a modulator.

Abstract: The present invention discloses active unit cell topologies for quasi-optic grid array structures that make use of combinations of one of several broadband or frequency-selective positive (or regenerative) feedback networks, as well as multiple transistor configurations in order to enhance the gain of the grid array amplifier. These new topologies yield higher gain, extending the utility of the grid array amplifier to both new applications requiring higher gain, as well as to higher frequencies where the intrinsic gain of the active devices is lower. They also offer greater flexibility in impedance matching, improving the bandwidth and manufacturability of the design.

Abstract: The present invention discloses an electronically frequency tunable and phase modulatable quasi-optic grid oscillator. The oscillator includes a reference signal input port whereby a small external reference signal is introduced that entrains the frequency and phase of the oscillator signal to it. Amplitude modulation techniques are introduced to further enhance the utility of the oscillator as a modulator.

Abstract: This invention relates to an improved heterojunction FET. More specifically the invention is directed to a heterojunction FET device in which the contact to the semiconductor gate is ohmic in character. The gate and channel regions of the FET have the same barrier height relative to an intervening third layer of semiconductor and sandwich the third layer of undoped semiconductor. The resulting symmetry of the structure provides a threshold voltage which lies normally near zero volts and is controllable upwardly or downwardly by adding an n or p type dopant to the undoped third layer or region.

Abstract: A quantity of silicon serving as a source of the element silicon for use in a molecular beam epitaxial growth apparatus where the silicon is in the form of a monocrystalline wafer with a plurality of electrically parallel filaments separated by slots that pass completely through the wafer, each filament having a length dimension that is greater than the width and height dimensions, joined at a broad contact area at each filament end and where an electric current is passed through the filaments through the broad contact areas.