Patents by Inventor James Jacob Riling

James Jacob Riling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8418012
    Abstract: A method of testing a target electronic device implemented in a configurable integrated circuit device includes receiving a baseline design for the target electronic device in a hardware description language, establishing a fault model for the particular configurable integrated circuit device, synthesizing the fault model in the hardware description language, embedding the synthesized fault model into the baseline design to create a modified baseline design in the hardware description language which enables one or more targeted signals to be selectively corrupted, creating a fault model enabled target device on the particular configurable integrated circuit device using the modified baseline design, performing a number of fault injection experiments on the fault model enabled target device, wherein each fault injection experiment includes causing at least one of the one or more targeted signals to be corrupted within the fault model enabled target device.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: April 9, 2013
    Assignee: Ansaldo STS USA, Inc.
    Inventors: Kevin Joseph Blostic, James Jacob Riling, Adam Edward Szymkowiak, Todd Anthony DeLong, Joseph William Reutzel, Anthony Pietro Mancini, II
  • Publication number: 20120216091
    Abstract: A method of testing a target electronic device implemented in a configurable integrated circuit device includes receiving a baseline design for the target electronic device in a hardware description language, establishing a fault model for the particular configurable integrated circuit device, synthesizing the fault model in the hardware description language, embedding the synthesized fault model into the baseline design to create a modified baseline design in the hardware description language which enables one or more targeted signals to be selectively corrupted, creating a fault model enabled target device on the particular configurable integrated circuit device using the modified baseline design, performing a number of fault injection experiments on the fault model enabled target device, wherein each fault injection experiment includes causing at least one of the one or more targeted signals to be corrupted within the fault model enabled target device.
    Type: Application
    Filed: September 21, 2011
    Publication date: August 23, 2012
    Applicant: Ansaldo STS USA, Inc.
    Inventors: Kevin Joseph Blostic, James Jacob Riling, Adam Edward Szymkowiak, Todd Anthony DeLong, Joseph William Reutzel, Anthony Pietro Mancini, II
  • Patent number: 5916289
    Abstract: A SIR system has frontal air bags and side air bags both controlled by the same microprocessor. To guard against spurious deployment of side air bags with minimal software burden, a lateral accelerometer and an arming circuit detect side crash activity and apply an arming signal to a pulse accumulator circuit in the microprocessor which monitors the accumulator state to detect arming, thereby inhibiting deployment when the arming signal is absent. The arming circuit receives the accelerometer signal, removes the dc component which is subject to drift, adds a fixed offset voltage and compares the resultant signal to threshold values to produce an arming signal when a threshold is breached.
    Type: Grant
    Filed: February 10, 1997
    Date of Patent: June 29, 1999
    Assignee: Delco Electronics Corp.
    Inventors: Salem Ahmad Fayyad, Sheri Lynn Patterson, Troy Allen Wideman, James Jacob Riling